本文關鍵詞： 電荷俘獲型存儲器 模型 模擬　出處：《蘭州大學》2012年碩士論文　論文類型：學位論文

【摘要】：隨著非揮發(fā)存儲器進入20nm工藝節(jié)點,傳統(tǒng)的基于多晶硅浮柵結構的存儲器在結構性能上遇到很多限制,其中最重要的問題是由于器件可靠性導致的尺寸無法按照等比例縮小的原則繼續(xù)推進。為此,研究者們提出了多種新的揮發(fā)存儲器結構,具有擦寫速度快、可靠性高、制作工藝簡單、成本低、與傳統(tǒng)CMOS工藝完全兼容等優(yōu)點的電荷俘獲存儲器以其分立存儲的特性,成為多晶硅浮柵結構的最有潛力的替代方案之一。然而,目前電荷俘獲存儲器的研究中仍有許多問題需要解決。 本論文首先回顧了非揮發(fā)性浮柵存儲器的工作原理以及其在可微縮化發(fā)展上所面臨的挑戰(zhàn),提出電荷俘獲存儲器的產生背景、發(fā)展歷程以及工作原理。通過對電荷俘獲存儲器各功能層研究進展的分析和總結,指出了目前研究中存在的問題以及可能的解決方案。 論文對基于氮化硅存儲層的電荷俘獲型存儲器中涉及到的物理機理及物理模型,包括襯底電子進入存儲層的各種隧穿方式、存儲層陷阱能級在實空間和能量空間上的分布、電荷在存儲層材料(氮化硅)中的遷移率、電荷的俘獲及釋放過程等做了詳細分析,并在模擬過程中做了針對性的選擇或處理。器件在編程和擦除操作時隧穿氧化層中的電場較大,通過陷阱輔助隧穿進入存儲層的幾率較小,在模擬中可不需考慮。在存儲層陷阱能級的分布上,實驗報道的能級分布有高斯分布、指數分布等等,但其分布的能級范圍都很窄,所以可將其看作是單一的能級分布。對于被俘獲的電荷從陷阱能級中的釋放過程(機理),結合兩性陷阱模型與Poole-Frenkel效應,本文對此做了詳細的分析與討論,給出了一種較為合理的模型解釋,并將其用于數值模擬。 將上述涉及到的模型方程加入電荷在存儲層中輸運的漂移-擴散方程和電流連續(xù)性方程中,形成耦合的方程組,通過對存儲層網格化的方法將其離散,并利用牛頓迭代的方法對方程組進行求解,模擬了存儲器的編程、擦除特性以及數據保持特性。 本論文也研究了功能層厚度、陷阱參數等對器件特性的影響。SONOS結構存儲器的編程速度隨著隧穿層的厚度的增加而下降,但在隧穿層與阻擋層總的厚度不變的情況下,改變隧穿層的厚度對器件的編程速度沒有影響；而對于TANOS結構,增大阻擋層的厚度并沒有對器件的數據保持特性帶來很大的改善,這驗證了隧穿氧化層是數據保持狀態(tài)下電荷泄漏的主要途徑。對于文獻中給出的不同的陷阱能級深度,我們對其編程和擦除特性進行了模擬,結果發(fā)現編程速度幾乎沒有變化,而擦除速度隨著陷阱能級深度的減小而增加,主要的原因應該是更淺的陷阱能級深度導致了擦除時存儲層陷阱中電荷釋放到導帶的數量增加。
[Abstract]:With the non-volatile memory entering the 20nm process node, the traditional memory based on the polysilicon floating gate structure has many limitations on the performance of the structure. The most important problem is that the size of the device can not be reduced according to the principle of equal proportion. Therefore, researchers have proposed a variety of new volatile memory structures, which have high speed of erasing. The charge-trapping memory, which has the advantages of high reliability, simple fabrication process, low cost and compatible with the traditional CMOS process, has the characteristics of discrete storage. It has become one of the most promising alternatives to polysilicon floating gate structure. However, there are still many problems to be solved in the research of charge capture memory. In this paper, the working principle of non-volatile floating gate memory and the challenges it faces in the development of scalable floating gate memory are reviewed, and the background of charge capture memory is proposed. Based on the analysis and summary of the research progress of the charge capture memory function layer, the existing problems and possible solutions are pointed out. The physical mechanism and physical models involved in charge capture memory based on silicon nitride storage layer, including various tunneling modes of substrate electrons entering the memory layer, are discussed in this paper. The distribution of trap energy levels in real space and energy space, the mobility of charge in storage layer material (silicon nitride), the capture and release process of charge are analyzed in detail. The electric field in the oxide layer of tunneling is larger during programming and erasure operation, and the probability of tunneling into the storage layer through trap assisted tunneling is small. There is no need to consider in the simulation. In the storage layer trap level distribution, the experimental energy level distribution includes Gao Si distribution, exponential distribution and so on, but the energy level distribution range is very narrow. Therefore, it can be regarded as a single energy level distribution. For the release process of trapped charge from trap level (mechanism, combined with amphoteric trap model and Poole-Frenkel effect). This paper makes a detailed analysis and discussion, gives a more reasonable model explanation, and applies it to numerical simulation. The model equations mentioned above are added to the drift-diffusion equation and the current continuity equation of charge transport in the storage layer to form the coupled equations and to discretize them by gridding the storage layer. Newton iterative method is used to solve the equations, and the memory programming, erasure characteristics and data retention characteristics are simulated. This thesis also studies the influence of the thickness of function layer and trap parameters on the device characteristics. The programming speed of SONOS structure memory decreases with the increase of tunneling layer thickness. However, when the total thickness of the tunneling layer and the barrier layer is constant, changing the thickness of the tunneling layer has no effect on the programming speed of the device. For the TANOS structure, increasing the thickness of the barrier layer does not improve the data retention characteristics of the device. This verifies that the tunneling oxide layer is the main way of charge leakage in the data holding state. For the different trap energy levels given in the literature, we simulate its programming and erasure characteristics. The results show that the programming speed is almost unchanged, and the erasure speed increases with the decrease of trap level depth. The main reason is that the shallow trap level depth leads to an increase in the amount of charge released to the conduction band in the storage trap during erasure.
【學位授予單位】：蘭州大學
【學位級別】：碩士
【學位授予年份】：2012
【分類號】：TP333

【參考文獻】

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1 鄭志威;霍宗亮;朱晨昕;許中廣;劉t，

本文編號：1464023