本文關(guān)鍵詞： FPGA 浮點加減法運算 控制器 多操作數(shù)　出處：《計算機測量與控制》2014年09期 　論文類型：期刊論文

【摘要】：為實現(xiàn)一種能夠自主完成浮點數(shù)加/減運算功能的浮點數(shù)加/減運算執(zhí)行控制器,提出了一種基于采用FPGA并行操作電路硬連接的浮點數(shù)加/減運算控制電路及其時序控制方法;該控制器在接收到操作數(shù)類型與參與運算的操作數(shù)后,在內(nèi)部時序脈沖作用下.可以自主完成操作數(shù)的配置以及浮點數(shù)加/減法運算的功能,運算結(jié)果傳輸?shù)较到y(tǒng)數(shù)據(jù)總線;論述了該控制器的電路構(gòu)成和基本原理,分析操作數(shù)類型與操作數(shù)在內(nèi)部時序脈沖作用下的執(zhí)行過程,應(yīng)用Verilog HDL語言實現(xiàn)相關(guān)硬件的構(gòu)建和連接;設(shè)計完成后通過仿真測試可知,該控制器運行的最高頻率可達178.317 M,從輸入端口到輸出端口的延時數(shù)據(jù)為:最小延時是3.185 ns,最大延時是15.336 ns,耗用的IO輸入輸出端口占總資源的27.92%,數(shù)據(jù)表明該控制器提高了運算器的運算速度,且能夠自主完成浮點數(shù)加/減運算。
[Abstract]:In order to realize a floating-point addition / subtraction execution controller which can independently complete the floating-point addition / subtraction function. A floating-point addition / subtraction control circuit based on hard connection of FPGA parallel operation circuit and its timing control method are proposed. After receiving the Operand type and the operands participating in the operation, the controller can independently complete the configuration of the Operand and the function of the floating-point addition / subtraction under the action of the internal sequential pulse. The operation result is transmitted to the system data bus; The circuit structure and basic principle of the controller are discussed, and the implementation process of Operand type and Operand under the action of internal sequential pulse is analyzed. Using Verilog HDL language to realize the construction and connection of related hardware; After the design is finished, the simulation results show that the maximum frequency of the controller can reach 178.317 M.The delay data from the input port to the output port are as follows: the minimum delay is 3.185 ns. The maximum delay is 15.336 ns, and the IO input and output ports consumed account for 27.92% of the total resources. The data show that the controller improves the speed of the processor. And can independently complete floating point addition / subtraction operation.
【作者單位】： 廣西科技大學電氣與信息工程學院;
【基金】：廣西科學基金(桂科自2011GXNSFAO18153)
【分類號】：TP332
【正文快照】： o引言 晚:產(chǎn)白產(chǎn)姑科粉描、-貧結(jié)許面+始T郵坦宜知粉估隨著信息應(yīng)用領(lǐng)域?qū)?shù)據(jù);?算精度要求的不斷提高和數(shù)值、-姑“廿田丁ms上還算范圍的不斷擴大,使得浮點:?算的研究越來越重要。浮點曰|┦，

本文編號：1459865