本文關(guān)鍵詞： 眾核處理器 拓?fù)渲貥?gòu) 行波列借 成團(tuán)效應(yīng) 可靠性　出處：《東華大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

【摘要】：隨著半導(dǎo)體技術(shù)進(jìn)入納米時(shí)代，受功耗、互連線延遲、設(shè)計(jì)復(fù)雜度等因素限制，芯片設(shè)計(jì)技術(shù)已從傳統(tǒng)的高復(fù)雜度單核處理器模式轉(zhuǎn)向在片上集成眾多相對(duì)簡(jiǎn)單內(nèi)核的模式；處理器設(shè)計(jì)進(jìn)入了眾核處理器時(shí)代。但是，一方面受生產(chǎn)缺陷、工藝偏差的影響，另一方面隨著眾核處理器芯片上內(nèi)核數(shù)量的不斷增加，這都將增加芯片上出現(xiàn)失效核的風(fēng)險(xiǎn)，進(jìn)而導(dǎo)致芯片成品率降低。因此，如何提高芯片成品率已成為產(chǎn)業(yè)界和學(xué)術(shù)界的熱點(diǎn)問(wèn)題。 核級(jí)冗余技術(shù)是提高眾核處理器成品率的一種有效方法�，F(xiàn)有的行波列借拓?fù)渲貥?gòu)算法是基于分級(jí)優(yōu)化思想，把整體優(yōu)化問(wèn)題分解為以失效核為中心的局部?jī)?yōu)化問(wèn)題，然后通過(guò)局部搜索失效核重構(gòu)的最優(yōu)解來(lái)求解整體優(yōu)化問(wèn)題的最優(yōu)解。但是，其在局部鄰域進(jìn)行的是單向搜索，易導(dǎo)致搜索到的解并不是局部最優(yōu)解，或者前一單元依次占用下一單元最優(yōu)解而導(dǎo)致連鎖列借操作。針對(duì)這種情況，本文構(gòu)造了一種局部鄰域雙向搜索的優(yōu)化行波列借算法，，使得局部解更優(yōu)并避免了連鎖操作。實(shí)驗(yàn)表明，在失效核數(shù)目較多的情況下，本算法所得拓?fù)浣Y(jié)構(gòu)的性能要明顯好于原有行波列借算法所得。 為了滿足眾核系統(tǒng)在安全關(guān)鍵領(lǐng)域的適用需求，本文提出了以可靠性為優(yōu)化目標(biāo)的眾核處理器核級(jí)冗余拓?fù)渲貥?gòu)模擬退火算法。該算法首先針對(duì)2D-Mesh拓?fù)浣Y(jié)構(gòu)的眾核處理器進(jìn)行了可靠性建模；并采用匕首抽樣的蒙特卡洛方法進(jìn)行可靠性仿真計(jì)算；最后采用模擬退火優(yōu)化技術(shù)實(shí)現(xiàn)該眾核處理器核級(jí)冗余拓?fù)渲貥?gòu)算法。通過(guò)實(shí)驗(yàn)對(duì)比得出：當(dāng)2D-Mesh網(wǎng)絡(luò)中鏈路可靠性較高時(shí)物理拓?fù)浣Y(jié)構(gòu)對(duì)整個(gè)眾核處理器可靠性的影響不大，因此在計(jì)算眾核處理器可靠性時(shí)只需考慮處理器核節(jié)點(diǎn)的故障成團(tuán)效應(yīng)對(duì)系統(tǒng)可靠性的影響即可。實(shí)驗(yàn)還與當(dāng)前以性能為優(yōu)化目標(biāo)的拓?fù)渲貥?gòu)算法進(jìn)行比較，結(jié)果表明在失效核數(shù)目較少時(shí)，新的算法可以大幅提高眾核處理的可靠性。 本文對(duì)眾核處理器核級(jí)冗余拓?fù)渲貥?gòu)這一NP-Complete類問(wèn)題實(shí)例進(jìn)行了近似和啟發(fā)式方法的求解嘗試，獲得的研究結(jié)果可為以性能和可靠性為優(yōu)化目標(biāo)的眾核處理器核級(jí)冗余拓?fù)渲貥?gòu)方案設(shè)計(jì)提供借鑒或支持。
[Abstract]:As semiconductor technology enters the nanometer age, it is limited by power consumption, interconnect delay, design complexity and so on. The chip design technology has changed from the traditional single-core processor mode with high complexity to the mode of integrating many relatively simple cores on the chip. Processor design has entered the era of multi-core processor. However, on the one hand, due to production defects, process bias, on the other hand, with the increasing number of cores on the multi-core processor chip. This will increase the risk of failure core on the chip, and then lead to the reduction of the yield of the chip. Therefore, how to improve the yield of the chip has become a hot issue in industry and academia. Nuclear redundancy is an effective method to improve the yield of multi-core processors. Existing traveling wave train topology reconstruction algorithms are based on hierarchical optimization. The global optimization problem is decomposed into a local optimization problem centered on the failure kernel, and then the optimal solution of the global optimization problem is solved by local searching the optimal solution of the failure kernel reconstruction. The local neighborhood is a one-way search, which is easy to lead to the search solution is not the local optimal solution, or the former unit in turn occupy the next unit optimal solution, leading to chain sequence borrowing operation. In this paper, an optimal traveling wave train borrowing algorithm based on local neighborhood bidirectional search is constructed, which makes the local solution better and avoids the linkage operation. The experimental results show that the number of failure cores is large. The performance of the proposed algorithm is better than that of the original traveling wave train algorithm. In order to meet the needs of the multi-nuclear system in the security critical areas. In this paper, a simulated annealing algorithm for core level redundant topology reconstruction of multi-core processors with reliability as the optimization objective is proposed. Firstly, the reliability modeling of the multi-core processors with 2D-Mesh topology is carried out. The Monte Carlo method of dagger sampling is used to simulate the reliability. Finally, simulated annealing optimization technique is used to realize the core level redundant topology reconstruction algorithm of the multi-core processor. When the link reliability is high in 2D-Mesh network, the physical topology has little effect on the reliability of the whole multi-core processor. Therefore, in computing the reliability of multi-core processor, we only need to consider the effect of the cluster effect of the processor core node on the reliability of the system. The experiment is also compared with the current topology reconstruction algorithm based on performance optimization. The results show that the new algorithm can greatly improve the reliability of multi-kernel processing when the number of failure cores is small. In this paper, we try to solve the NP-Complete class problem by using approximate and heuristic methods to reconstruct the core level redundant topology of the multi-core processor. The results can be used for reference or support for the design of core level redundant topology reconstruction scheme of multi-core processor with performance and reliability as the optimization objective.
【學(xué)位授予單位】：東華大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TP332

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