本文關(guān)鍵詞： DSP 串行通信接口 地址預(yù)測 功能驗(yàn)證 覆蓋率　出處：《江南大學(xué)》2013年碩士論文　論文類型：學(xué)位論文

【摘要】：數(shù)字信號處理技術(shù)已經(jīng)在我們的生活中變得非常普及,其重要性在通信、語音和圖像處理、航空航天、汽車電子等各個領(lǐng)域的應(yīng)用中日益凸顯。為了提供更快的處理速度和更為豐富的功能,系統(tǒng)集成化成為數(shù)字信號處理器(Digital Signal Processor, DSP)芯片的一個明確的發(fā)展趨勢。為滿足不同場合的應(yīng)用,DSP芯片通常都集成了豐富的通信接口。通信接口作為DSP芯片與外界進(jìn)行數(shù)據(jù)交換唯一通道,其性能也直接地影響了芯片的效率。 本文在分析現(xiàn)在通用的各種串行通信接口(McBSP、I2C、SPI和USB)特點(diǎn)的基礎(chǔ)上針對ZW100這款DSP芯片提出了一種新的uLink串行通信接口。uLink接口綜合了以上幾種的接口的一些特點(diǎn),加入了全握手過程、自動數(shù)據(jù)模式、地址預(yù)測以及分時復(fù)用通道等功能,能有效地提高數(shù)據(jù)傳輸效率。并在數(shù)據(jù)幀中加入了傳輸目標(biāo)地址,可以使數(shù)據(jù)接收方在數(shù)據(jù)接收過程中完全無需CPU的介入而將數(shù)據(jù)寫入目標(biāo)地址。 整個uLink的設(shè)計采用了VLSI設(shè)計中自頂向下的設(shè)計方法,根據(jù)功能進(jìn)行模塊劃分,利用硬件描述語言VHDL完成各個模塊的RTL級描述。使用SYNOPSYS公司的仿真工具VCS對設(shè)計進(jìn)行功能仿真,對仿真過程的覆蓋率參數(shù)進(jìn)行分析以保證驗(yàn)證結(jié)果的全面性和可靠性。以TSMC65納米工藝為目標(biāo)庫,利用Design Compiler對設(shè)計RTL代碼進(jìn)行邏輯綜合。對綜合結(jié)果采用Formality進(jìn)行形式驗(yàn)證,并用PrimeTime對綜合結(jié)果進(jìn)行設(shè)計時序驗(yàn)證。 仿真和時序驗(yàn)證結(jié)果表明：整個設(shè)計實(shí)現(xiàn)了所有預(yù)期功能,滿足uLink協(xié)議的所有要求。在500MHz的系統(tǒng)時鐘下,uLink接口能夠穩(wěn)定地工作,其理論最高通信速率可達(dá)125Mbit/s。目前該接口已成功集成于ZW100這款32位定點(diǎn)DSP芯片中。
[Abstract]:Digital signal processing technology has been in our life has become very popular, and its importance in communication, voice and image processing, aerospace, automotive and other applications in various fields has become increasingly prominent. In order to provide faster processing speed and more functions, system integration has become a digital signal processor (Digital Signal Processor, DSP) a clear trend of chip. In order to meet the application of different occasions, usually DSP chip integrated rich communication interface. Communication interface as DSP chip for data exchange only channel with the outside world, its performance directly affects the efficiency of the chip.
Based on the analysis of current various serial communication interface (McBSP, I2C, SPI and USB) based on the characteristics of the DSP chip on the ZW100 proposed a new uLink serial communication interface.ULink interface integrated some characteristics above the interface, with full automatic handshake process, data model, forecast and address when the multiplex channel function, can effectively improve the efficiency of data transmission. And joined the transfer destination address in the data frame, the receiver can make the data in the data receiving process without the intervention of CPU and writes the data to the destination address.
The top-down design method in the design of VLSI uLink using the design of the whole, is divided into several modules according to function, RTL the use of hardware description language VHDL module is described. Using the SYNOPSYS simulation tool VCS function simulation of the design, comprehensive coverage and reliability of parameter simulation process are analyzed to ensure the verification results using TSMC65 nano technology. The target database, logic synthesis is applied to design RTL code using Design Compiler. The results of synthesis using Formality for formal verification, and the results of comprehensive design timing verification with PrimeTime.
Simulation and timing verification results show that the design and implementation of all the expected functions, meet all the requirements of uLink protocol. The 500MHz system clock, uLink interface can work stably, its theoretical maximum communication speed can reach 125Mbit/s. at the interface has been successfully integrated into the ZW100 32 bit fixed-point DSP.

【學(xué)位授予單位】：江南大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TP334.7

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