本文關(guān)鍵詞：基于DVS的多核周期任務(wù)節(jié)能調(diào)度策略研究　出處：《武漢理工大學(xué)》2013年碩士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： 多核處理器 節(jié)能調(diào)度算法 動(dòng)態(tài)電壓調(diào)節(jié) 空閑時(shí)間

【摘要】：近年來,多核處理器在流媒體和高性能計(jì)算領(lǐng)域應(yīng)用廣泛。多核處理器與單核處理器相比帶來了更高的性能,但同時(shí)也帶來了更多的能耗,較高的能量消耗會(huì)導(dǎo)致處理器熱量的增加及系統(tǒng)可靠性的降低。節(jié)能性要求也必然存在于多核計(jì)算平臺上的應(yīng)用之中。 處理器能耗占系統(tǒng)總能耗的一半以上,處理器的能耗主要由動(dòng)態(tài)能耗和靜態(tài)泄露能耗構(gòu)成,一般情況下,動(dòng)態(tài)能耗占處理器總能耗的70%左右。根據(jù)當(dāng)前任務(wù)的能量消耗特性和多核系統(tǒng)結(jié)構(gòu),在滿足系統(tǒng)可靠性和截止期約束的前提下,如何減少能量消耗已成為多核處理器實(shí)時(shí)節(jié)能調(diào)度研究領(lǐng)域的熱點(diǎn)。 本文主要工作如下： (1)基于處理器核負(fù)載總均衡的思想,提出了PWBP任務(wù)映射策略,該策略將任務(wù)隊(duì)列中的任務(wù)按任務(wù)利用率從大到小排序,抽取前M個(gè)任務(wù)并將這M個(gè)任務(wù)輪詢映射到M個(gè)處理器核上,剩余的任務(wù)按順序映射到當(dāng)時(shí)負(fù)載最小的處理器核直至任務(wù)映射完成,此策略的核心思想是保持處理器核的總負(fù)載均衡,仿真實(shí)驗(yàn)表明該映射策略與其他映射策略相比有更好的節(jié)能效果；然后,基于周期任務(wù)的靜態(tài)空閑時(shí)間SST提出了MSSF最大靜態(tài)空閑時(shí)間優(yōu)先排序策略,在利用DVS技術(shù)回收動(dòng)態(tài)空閑時(shí)間之前,該策略對映射到處理器上的任務(wù)按靜態(tài)空閑時(shí)間SST的大小進(jìn)行重新排序,在單核處理器中,將MSSF排序策略與現(xiàn)有GSSR策略和STF策略對比,仿真實(shí)驗(yàn)結(jié)果表明了MSSF排序策略的優(yōu)越性。 (2)結(jié)合DVS技術(shù)中的HR2混合調(diào)度法,提出了PWBP-DSR節(jié)能調(diào)度算法,并根據(jù)最小關(guān)鍵速度Scritical增加了處理器速度判斷機(jī)制：當(dāng)處理器的速度S≤scritical時(shí)讓處理器的執(zhí)行速度S=Scritical如果處理器的速度ScriticalS≤1時(shí),則處理器按當(dāng)前速度S執(zhí)行任務(wù)。在此速度判斷機(jī)制的基礎(chǔ)上提出了改進(jìn)算法PWBP-DSR-M,將提出的改進(jìn)算法PWBP-DSR-M與參考文獻(xiàn)算法GEDF-OLEASA(ALL)和GEDF-OLEASA(EACH)對比,實(shí)驗(yàn)結(jié)果表明提出的改進(jìn)算法比其他兩種對比算法節(jié)能將近10%。
[Abstract]:In recent years, multicore processors have been widely used in streaming media and high-performance computing. Compared with single-core processors, multi-core processors bring higher performance, but also bring more energy consumption. Higher energy consumption will lead to the increase of processor heat and the decrease of system reliability. The requirement of energy saving must also exist in the application of multi-core computing platform. Processor energy consumption accounts for more than half of the total energy consumption of the system, the processor energy consumption is mainly composed of dynamic energy consumption and static leakage energy consumption, generally speaking. The dynamic energy consumption accounts for about 70% of the total energy consumption of the processor. According to the energy consumption characteristics of the current task and the multi-core system structure, the system reliability and deadline constraints are satisfied. How to reduce energy consumption has become a hotspot in the field of real-time energy-saving scheduling of multi-core processors. The main work of this paper is as follows: 1) based on the idea of total load balance of processor core, a PWBP task mapping strategy is proposed, which sorts the tasks in the task queue from large to small according to the task utilization. The first M tasks are extracted and the M tasks are polled onto M processor cores, and the remaining tasks are mapped sequentially to the processor cores with the smallest load at that time until the task mapping is completed. The core idea of this strategy is to maintain the total load balance of the processor core. The simulation results show that the mapping strategy has better energy saving effect than other mapping strategies. Then, the static idle time SST based on periodic task proposes the MSSF maximum static idle time priority ranking strategy, before using the DVS technology to recover the dynamic idle time. The policy reorders tasks mapped to the processor by the size of the static idle time SST, and compares the MSSF sort policy with the existing GSSR policy and the STF policy in a single core processor. Simulation results show the superiority of MSSF scheduling strategy. 2) combined with the HR2 hybrid scheduling method in DVS technology, a PWBP-DSR energy-saving scheduling algorithm is proposed. According to the minimum critical speed Scritical, the processor speed judgment mechanism is added. When the processor's speed S 鈮，

本文編號：1436377