發(fā)布時間：2018-01-16 03:29

  本文關(guān)鍵詞：C程序映射到FPGA的寄存器快速評估技術(shù)　出處：《小型微型計算機系統(tǒng)》2015年02期 　論文類型：期刊論文

  更多相關(guān)文章： FPGA 高級綜合 邏輯綜合 設(shè)計度量 寄存器快速評估

【摘要】：在基于FPGA的軟硬件協(xié)同設(shè)計中,對硬件面積和延遲時間進行快速準確地評估是快速生成片上異構(gòu)多處理器系統(tǒng)的關(guān)鍵步驟.使用傳統(tǒng)的邏輯綜合工具將會耗費大量的時間才能獲得面積-時間的度量值,導致在軟硬件協(xié)同設(shè)計流程中,抑制了設(shè)計空間的有效探索.本文關(guān)注將C程序映射到FPGA,對寄存器數(shù)量進行快速和準確的評估.提出的技術(shù)以高級綜合工具Leg Up和底層虛擬機LLVM為基礎(chǔ),利用信號位寬優(yōu)化信息、特殊指令信息以及編碼方式對寄存器進行評估.實驗結(jié)果表明,該技術(shù)能夠?qū)HStone基準測試程序進行寄存器數(shù)量的評估;以Altera CycloneⅡ和StratixⅣFPGA為平臺,實驗結(jié)果的誤差分別只有13.75%和10.48%,與使用Quartus工具的邏輯綜合運行時間相比,能夠?qū)崿F(xiàn)84倍的加速.
[Abstract]:In the hardware and software co-design based on FPGA. Fast and accurate evaluation of hardware area and delay time is a key step in fast generation of heterogeneous multiprocessor systems on a chip. Using traditional logic synthesis tools will take a lot of time to obtain area-time. Measure. As a result of hardware and software co-design process, the effective exploration of design space is restrained. This paper focuses on mapping C program to FPGA. The proposed technology is based on the advanced synthesis tool Leg up and the underlying virtual machine LLVM, and optimizes the information by using the signal bit width. The special instruction information and coding method are used to evaluate the register. The experimental results show that this technique can evaluate the number of registers for the CHStone benchmark program. Using Altera Cyclone 鈪，

本文編號：1431374