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多核片上互連方式研究

發(fā)布時(shí)間:2018-01-15 19:13

  本文關(guān)鍵詞:多核片上互連方式研究 出處:《南京大學(xué)》2017年碩士論文 論文類型:學(xué)位論文


  更多相關(guān)文章: 片上多核 互連結(jié)構(gòu) 交換方式 路由算法 片上網(wǎng)絡(luò)


【摘要】:隨著集成電路產(chǎn)業(yè)的發(fā)展,片上多核成為芯片發(fā)展的必然趨勢。高性能計(jì)算芯片也從運(yùn)算核心型轉(zhuǎn)為互連中心型。當(dāng)多處理器芯片的集成密度進(jìn)一步增加,與之相關(guān)聯(lián)的通信要求也越來越高。多核間通信方式的選擇成為影響系統(tǒng)性能的重要因素。當(dāng)前片內(nèi)互連結(jié)構(gòu)主要包含總線式互連及片上網(wǎng)絡(luò)互連,其中總線式互連區(qū)分為共享式總線和交叉開關(guān)式總線。為了得出各種互連方式的適用情況,本文分析不同互連結(jié)構(gòu)的優(yōu)勢和劣勢,并且用網(wǎng)絡(luò)負(fù)載仿真對(duì)資源使用和性能表現(xiàn)特點(diǎn)進(jìn)行模型分析。層次化交叉開關(guān)結(jié)構(gòu)和片上網(wǎng)絡(luò)能較好地解決共享總線等早期結(jié)構(gòu)的通信帶寬低和擴(kuò)展性差的問題。當(dāng)節(jié)點(diǎn)數(shù)目為中等規(guī)模時(shí),層次化交叉開關(guān)結(jié)構(gòu)在面積消耗和網(wǎng)絡(luò)負(fù)載方面較優(yōu);節(jié)點(diǎn)數(shù)目為大規(guī)模時(shí),片上網(wǎng)絡(luò)在網(wǎng)絡(luò)負(fù)載能力方面顯示了優(yōu)勢。此外數(shù)據(jù)的交換方式也會(huì)極大的影響數(shù)據(jù)帶寬和傳輸延時(shí)。按照是否建立專用路徑可以分為包交換方式和電路交換方式兩類。為了比較兩種交換方式下的網(wǎng)絡(luò)負(fù)載情況,本文采用RTL級(jí)設(shè)計(jì)研究網(wǎng)絡(luò)性能特點(diǎn)和片上資源開銷。當(dāng)網(wǎng)絡(luò)所傳輸?shù)臄?shù)據(jù)包很大時(shí),無論當(dāng)前數(shù)據(jù)注入率多大,包交換方式都會(huì)產(chǎn)生通道負(fù)載不均衡的問題,網(wǎng)絡(luò)性能下降嚴(yán)重。所以此時(shí)電路交換方式表現(xiàn)更優(yōu)。當(dāng)數(shù)據(jù)包尺寸中等時(shí),對(duì)于注入率低的情況,電路交換方式的性能表現(xiàn)更優(yōu);當(dāng)注入率升高時(shí),包交換方式能較好解決網(wǎng)絡(luò)擁堵的問題,從而展現(xiàn)出更好的性能。片上網(wǎng)絡(luò)包交換方式下的路由算法決定了數(shù)據(jù)包最終選擇哪條路徑從源地址傳到目的地址。本文的包交換片上網(wǎng)絡(luò)路由算法評(píng)估側(cè)重于分析網(wǎng)絡(luò)的吞吐率和平均時(shí)延?紤]和FFT運(yùn)算有關(guān)的梭型流量模式,適應(yīng)性的奇偶拐彎路由算法從平均時(shí)延和吞吐量上優(yōu)于靜態(tài)XY路由算法約15%;而在偽隨機(jī)流量模式下,奇偶拐彎路由算法對(duì)應(yīng)的拓?fù)渲虚g熱點(diǎn)問題突出,導(dǎo)致性能劣于靜態(tài)XY算法。
[Abstract]:With the development of the integrated circuit industry, multi-core chip has become the inevitable trend of development. The high performance computing chip from the operation core to interconnect center. When multi processor chip integration density further increased, and the associated communication requirements are increasingly high. Many inter core communication options become an important factor in the performance of the system. The on-chip interconnect structure includes bus interconnection network interconnection and on-chip bus interconnection, which is divided into shared bus and cross switched bus application. In order to draw all kinds of interconnection method, this paper analysis the advantages and disadvantages of different interconnection structure, and network load simulation of the use of resources and the performance characteristics of the model. A hierarchical crossbar structure and network on chip can solve the bandwidth shared communication bus structure and low expansibility early The problem of the poor. When the number of nodes is of medium size, a hierarchical crossbar structure in the area of consumption and the network load is better; the number of nodes is large, the on-chip network load capacity in the network shows the advantage. In addition to exchange data will greatly affect the data bandwidth and transmission delay. According to whether the establishment of the special path can be divided into packet switching and circuit switching mode of two kinds of load. In order to compare two kinds of exchange mode of the network, this paper adopts RTL Design Research on network performance characteristics and on-chip resources. When the network transmission of data packets is very large, regardless of the current injection rate in packet switching mode the channel will have the load balance problem, the decline of the network performance seriously. So the performance of circuit switching is better. When the packet size medium, the injection rate is low, the electric road Exchange performance way better; when the injection rate increased, packet switching can solve network congestion problems, which show better performance. The routing algorithm for network on chip under the packet switching mode determines the packet eventually choose which path from the source address to a destination address. The packet switched on in the analysis of network throughput and average delay evaluation of routing algorithms in network on chip. Considering the operation and FFT shuttle type flow model, adaptive routing algorithm is better than that of the odd even turn from the average delay and throughput of the static routing algorithm of XY is about 15%; and in the pseudo random flow model, topological middle hot issue routing algorithm corresponding to the odd even turn the outstanding result in performance is inferior to the static XY algorithm.

【學(xué)位授予單位】:南京大學(xué)
【學(xué)位級(jí)別】:碩士
【學(xué)位授予年份】:2017
【分類號(hào)】:TP332

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