發(fā)布時(shí)間：2018-01-15 04:19

  本文關(guān)鍵詞：基于2T GC的動(dòng)態(tài)隨機(jī)存儲(chǔ)器版圖設(shè)計(jì)及其關(guān)鍵參數(shù)表征與優(yōu)化　出處：《復(fù)旦大學(xué)》2012年碩士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： 嵌入式動(dòng)態(tài)隨機(jī)存儲(chǔ)器 雙管增益單元 存儲(chǔ)器版圖 單元保持漏電 數(shù)據(jù)保持時(shí)間

【摘要】：本文基于一種新型嵌入式動(dòng)態(tài)隨機(jī)存儲(chǔ)器2T GC的版圖設(shè)計(jì)和關(guān)鍵參數(shù)進(jìn)行了相關(guān)的研究工作。2T GC存儲(chǔ)器版圖設(shè)計(jì)是影響2T GC面積的重要因素,同時(shí)還涉及到面積與性能及功耗的折中問(wèn)題。其中包含了2T GC單元的版圖設(shè)計(jì)和優(yōu)化,主要考慮單元版圖對(duì)存儲(chǔ)密度和存儲(chǔ)性能的影響；陣列和行列驅(qū)動(dòng)電路版圖設(shè)計(jì),主要考慮大規(guī)模陣列的層次劃分問(wèn)題以及存儲(chǔ)陣列與外圍電路的拼接匹配；其它外圍電路版圖的布局和設(shè)計(jì),主要考慮各個(gè)模塊的布局以及大規(guī)模版圖設(shè)計(jì)時(shí)需要考慮的各種問(wèn)題。保持電流和數(shù)據(jù)保持時(shí)間是影響2T GC靜態(tài)保持功耗和性能的兩個(gè)主要參數(shù),而且在新工藝代下漏電流和波動(dòng)性問(wèn)題日益凸顯,本文基于65nm工藝代針對(duì)2T GC的兩大關(guān)鍵參數(shù)保持漏電流和數(shù)據(jù)保持時(shí)間波動(dòng)性的表征問(wèn)題進(jìn)行了研究,其中對(duì)保持電流的研究主要包括單元保持漏電的來(lái)源分析,以及陣列和單元保持漏電表征方案及單元保持漏電的優(yōu)化方案分析,同時(shí)將提出的表征方案應(yīng)用于靜態(tài)隨機(jī)存儲(chǔ)器SRAM的單元漏電表征。2T GC是動(dòng)態(tài)隨機(jī)存儲(chǔ)器即需要周期性刷新,而刷新周期則是由單元的數(shù)據(jù)保持時(shí)間決定的,所以2T GC數(shù)據(jù)保持時(shí)間是影響刷新功耗和存儲(chǔ)性能的重要參數(shù),而在新工藝代下此參數(shù)受PVT工藝波動(dòng)影響會(huì)產(chǎn)生相應(yīng)的波動(dòng)變化,為了研究此波動(dòng)情況從而給芯片設(shè)計(jì)參數(shù)制定提供指導(dǎo)本文提出了一種表征2T GC數(shù)據(jù)保持時(shí)間波動(dòng)性的方案。 本文最終基于SMIC0.13um工藝實(shí)現(xiàn)了一款128kb的2T GC存儲(chǔ)器芯片,經(jīng)過(guò)驗(yàn)證具有正確的讀寫功能；同時(shí)本文還基于SMIC65nm工藝實(shí)現(xiàn)了2T GC單元保持漏電和數(shù)據(jù)保持時(shí)間的表征。
[Abstract]:The layout design and the key parameters of a new embedded dynamic random access memory 2T based on GC the design work of.2T GC memory layout is an important factor that affects the 2T GC area, but also involves a tradeoff between area and performance and power consumption. Which includes the design and optimization of the layout of 2T GC unit, the main consideration effect of storage cell layout density and storage performance; circuit layout design drive array and ranks, mainly consider the hierarchy of large-scale array and splicing memory array and peripheral circuit, other peripheral circuit layout; layout and design, all kinds of problems need to be considered the main consideration of each module layout and scale layout design. The current and the data retention time are two main parameters affecting 2T GC static power consumption and performance, but also in the process of the new generation Leakage current and volatility problems have become increasingly prominent, the 65nm process on behalf of two key parameters for 2T GC to keep the leakage current and maintain data representation of time variability was studied based on the research to maintain the current mainly includes the analysis of leakage source unit remains, and keep the unit array and the leakage characterization scheme and unit analysis of optimization scheme of leakage, while the proposed characterization scheme is applied to static random access memory SRAM cell leakage characterization of.2T GC dynamic random access memory that requires periodic refresh, refresh cycle is from the unit and the data retention time of decision, so 2T GC data hold time is an important parameter affecting the refresh power and storage performance in the process, the new generation of the parameters affected by PVT process fluctuations will produce fluctuations corresponding to the situation, so as to study the fluctuation of chip The design parameter formulation provides guidance and proposes a scheme to characterize the time volatility of 2T GC data retention.
Finally, a 128KB 2T GC memory chip is implemented based on SMIC0.13um technology. After verification, it has the correct read and write function. At the same time, based on the SMIC65nm technology, the 2T GC unit maintains the leakage and data retention time.

【學(xué)位授予單位】：復(fù)旦大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TP333

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本文編號(hào)：1426762