本文關(guān)鍵詞：面向臉部特征檢測的嵌入式多核架構(gòu)研究　出處：《天津大學(xué)》2012年碩士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： 特征檢測 并行體系結(jié)構(gòu) 可配置可擴展處理器 軟硬件協(xié)同設(shè)計

【摘要】：作為近年來的熱點研究問題,視線估計的重要意義逐漸被越來越多的人們意識到,同時它也是本課題組多年來的主要研究方向。臉部特征提取作為視線估計系統(tǒng)中的重要組成部分是本文將要研究的重點內(nèi)容。根據(jù)課題組對此領(lǐng)域的研究發(fā)現(xiàn),計算效率高并且資源消耗低的嵌入式臉部特征實時檢測系統(tǒng)是研究趨勢。本文使用軟硬件協(xié)同設(shè)計方法,并且基于傳輸觸發(fā)架構(gòu)可配置可擴展處理器(T*CORE)對此領(lǐng)域的一系列問題展開研究。 本文在處理流程上放棄了原有的利用膚色的檢測算法而采用了檢測精度更高的基于haar-like特征的人臉檢測算法,同時優(yōu)化YCbCrCg膚色分割模型使得計算量降低到原有的1/3,并且提出改進(jìn)的積分圖和平方積分圖的數(shù)據(jù)存儲格式來減少算法計算期間占用大量存儲空間的問題,使得數(shù)據(jù)寬度縮減到17bits和25bits。并且本文提出一個新穎的人臉檢測并行策略,即在相同尺寸的圖像下連續(xù)檢測窗口中相同位置的弱分類器同時計算,在提高計算速度的同時又沒有增加寄存器資源消耗。 根據(jù)對算法的功能劃分,本文采用了基于傳輸觸發(fā)架構(gòu)的可配置可擴展處理器架構(gòu)實現(xiàn)人臉檢測功能,針對具體應(yīng)用設(shè)計了10個功能單元和對應(yīng)的并行程序。而其它模塊則分別在ASIC模塊和NIOSⅡ上實現(xiàn),并在此基礎(chǔ)上提出基于SOPC平臺的多核架構(gòu)。整個系統(tǒng)的運行頻率為100MHz,在檢測圖像尺寸為640*480的情況下處理速度達(dá)到8fps,滿足最初的設(shè)計需求。
[Abstract]:As a hot research issue in recent years, the importance of line of sight estimation has been gradually recognized by more and more people. At the same time, it is also the main research direction of our group for many years. As an important part of the line of sight estimation system, facial feature extraction is the focus of this paper. Embedded face feature real-time detection system with high computing efficiency and low resource consumption is the research trend. This paper uses hardware and software co-design method. A series of problems in this field are studied based on the configurable extensible processor (TX) based on the transport trigger architecture. In this paper, the original skin color detection algorithm is abandoned in the processing process, and the face detection algorithm based on haar-like features with higher detection accuracy is adopted. At the same time, the YCbCrCg skin segmentation model is optimized to reduce the computational complexity to the original 1/3. An improved data storage format of integral graph and square integral graph is proposed to reduce the large amount of storage space during the computation of the algorithm. The data width is reduced to 17 bits and 25 bits. A novel parallel face detection strategy is proposed in this paper. The weak classifier of the same position in the continuous detection window is calculated simultaneously under the same image size, which not only increases the speed of calculation but also does not increase the consumption of register resources. According to the functional partition of the algorithm, this paper uses a configurable scalable processor architecture based on transmission trigger architecture to implement face detection. Ten functional units and corresponding parallel programs are designed for specific applications, while other modules are implemented on ASIC module and NIOS 鈪，

本文編號：1424610