本文關(guān)鍵詞：基于LSI的多種類ISA處理器平臺(tái)設(shè)計(jì)與研究　出處：《南京大學(xué)》2012年碩士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： ISA處理器 LSI FPGA Wishbone

【摘要】：隨著社會(huì)的不斷發(fā)展,不僅在工業(yè)生產(chǎn),而且在人們的普通生活中,對(duì)于精密控制的需求越來(lái)越大。而傳統(tǒng)ISA處理器由于其內(nèi)部有限的邏輯資源和外部固定的引腳封裝,大大的限制了它的應(yīng)用范圍。由于市場(chǎng)上有著各具特色的微處理器,為了能很好的學(xué)習(xí)它們,我們不得不購(gòu)買大量不同的平臺(tái),造成資源的浪費(fèi)。 本文首先通過(guò)詳細(xì)的分析傳統(tǒng)的微處理器組成結(jié)構(gòu)、存儲(chǔ)器組織結(jié)構(gòu)和指令集結(jié)構(gòu),使我們對(duì)于處理器工作原理有了明確的認(rèn)識(shí)。接著分析基于LSI的可編程ASIC器件FPGA的內(nèi)部結(jié)構(gòu),發(fā)現(xiàn)我們可以充分利用FPGA豐富的邏輯資源來(lái)實(shí)現(xiàn)傳統(tǒng)MCU中的各個(gè)組成部分,而它的可配置引腳將會(huì)幫助降低硬件設(shè)計(jì)復(fù)雜度,最后我們論述了Wishbone總線結(jié)構(gòu),用來(lái)作為各個(gè)模塊間相互連接總線。 使用該種方式構(gòu)建系統(tǒng),對(duì)于上層軟件工程師而言其編程操作與標(biāo)準(zhǔn)MCU相一致,而對(duì)于底層可以自由配置IO引腳,獲得最大的硬件自由度。我們采用了片內(nèi)總線設(shè)計(jì),因此我們可以依據(jù)自己的需求,定制自己的系統(tǒng),如增加各種外設(shè),以達(dá)到傳統(tǒng)MCU所無(wú)法完成的要求。對(duì)于高校,可以使用這種方法來(lái)進(jìn)行教學(xué)實(shí)驗(yàn),能夠讓學(xué)生深入的理解MCU中每個(gè)組成部分的功能和它的連接方式,同時(shí)也不會(huì)造成硬件損壞。 本文使用硬件描述語(yǔ)言Verilog和VHDL,自底向上設(shè)計(jì)MIPS、8086、80C51和AVR處理核心,并且與幾類通用外設(shè)互連組成系統(tǒng),使用Virtex-Ⅱ Pro系歹FPGA進(jìn)行板級(jí)驗(yàn)證。板級(jí)驗(yàn)證結(jié)果,表明我們實(shí)現(xiàn)既定目標(biāo),與標(biāo)準(zhǔn)MCU兼容,系統(tǒng)運(yùn)行穩(wěn)定。
[Abstract]:With the continuous development of society, not only in industrial production, but also in the ordinary life of people. The demand for precision control is increasing, while the traditional ISA processor is encapsulated because of its limited internal logic resources and external fixed pins. Because of the unique microprocessor in the market, in order to learn them well, we have to buy a large number of different platforms, resulting in a waste of resources. Firstly, this paper analyzes the traditional microprocessor structure, memory organization structure and instruction set structure in detail. So that we have a clear understanding of the working principle of the processor. Then the internal structure of the programmable ASIC device FPGA based on LSI is analyzed. It is found that we can make full use of the rich logic resources of FPGA to realize each component of traditional MCU, and its configurable pin will help reduce the complexity of hardware design. Finally, we discuss the structure of Wishbone bus, which is used to connect each module to each other. Building systems in this way is consistent with standard MCU programming for upper software engineers and free to configure IO pins for the bottom layer. Get the maximum degree of freedom of hardware. We use an in-chip bus design, so we can customize our own system according to our own needs, such as adding a variety of peripherals. In order to achieve the traditional MCU can not complete the requirements. For colleges and universities, we can use this method to carry out teaching experiments, so that students can deeply understand the function of each component of MCU and its connection. Also does not cause hardware damage. In this paper, we use hardware description languages Verilog and VHDL to design the MIPS 8086 / 80C51 and AVR processing cores from the bottom up, and interconnect with several kinds of general peripheral devices to make up the system. Using Virtex- 鈪，

本文編號(hào)：1412569