本文關(guān)鍵詞：先進(jìn)微處理器高密度封裝協(xié)同設(shè)計(jì)與仿真技術(shù)研究　出處：《國防科學(xué)技術(shù)大學(xué)》2013年碩士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： 先進(jìn)微處理 高密度封裝 信號完整性 電源完整性 協(xié)同設(shè)計(jì)

【摘要】：封裝是微處理器的重要組成部分，它作為芯片與外界的連接橋梁，對于整個系統(tǒng)的性能發(fā)揮具有非常重要的作用。隨著集成電路技術(shù)的發(fā)展，現(xiàn)代先進(jìn)微處理器的輸入輸出接口快速增長，使得封裝呈現(xiàn)出高密度的特點(diǎn)。傳統(tǒng)的封裝設(shè)計(jì)方法逐漸顯露出設(shè)計(jì)難度增大、無法達(dá)到設(shè)計(jì)要求和過設(shè)計(jì)等問題，成為限制微處理器設(shè)計(jì)發(fā)展的一個瓶頸。 本文基于“核高基”重大專項(xiàng)高性能微處理器項(xiàng)目，針對先進(jìn)微處理器高密度封裝設(shè)計(jì)中存在的問題，研究協(xié)同設(shè)計(jì)與仿真技術(shù)，分別研究了多階段協(xié)同、信號與電源完整性協(xié)同和設(shè)計(jì)與仿真協(xié)同技術(shù)，具體包括： (1)封裝驅(qū)動的多階段協(xié)同設(shè)計(jì)規(guī)劃。針對傳統(tǒng)設(shè)計(jì)方法中芯片、封裝和電路板獨(dú)立設(shè)計(jì)存在的不足，本文提出將三者作為一個整體協(xié)同設(shè)計(jì)，，并以封裝為中心對系統(tǒng)進(jìn)行統(tǒng)一的引腳分配，以解決信號引腳分配不合理、走線不順、布局混亂等問題。 (2)基于疊層規(guī)劃的信號與電源協(xié)同設(shè)計(jì)。高密度封裝中信號與電源的相互影響愈加嚴(yán)重，本文提出在疊層規(guī)劃中同時考慮信號完整性和電源完整性，對信號和電源進(jìn)行協(xié)同設(shè)計(jì)，減小在封裝設(shè)計(jì)中信號與電源相互影響，使二者達(dá)到最佳。 (3)面向封裝的設(shè)計(jì)與仿真協(xié)同優(yōu)化。為了解決傳統(tǒng)設(shè)計(jì)中使用經(jīng)驗(yàn)法則等粗放型設(shè)計(jì)方法存在的不足，本文提出將設(shè)計(jì)與仿真緊密結(jié)合，在設(shè)計(jì)之初通過仿真制定準(zhǔn)確的設(shè)計(jì)規(guī)則和目標(biāo)，在設(shè)計(jì)之后用仿真驗(yàn)證設(shè)計(jì)，通過精細(xì)化方法解決欠設(shè)計(jì)和過設(shè)計(jì)問題。 基于以上協(xié)同設(shè)計(jì)方法，本文設(shè)計(jì)實(shí)現(xiàn)了一款先進(jìn)微處理器的高密度封裝。該處理器主要包括DDR3、PCIE、SATA等12種接口和7種電源，芯片引腳數(shù)達(dá)到4733。采用本文提出的方法，設(shè)計(jì)實(shí)現(xiàn)了尺寸為42.5mm×42.5mm和封裝引腳為1572個的處理器芯片封裝。實(shí)測結(jié)果表明，該封裝芯片可穩(wěn)定工作在1.2GHz，DDR、PCIE和SATA速率分別達(dá)到1333Mbps、5.0Gbps和3.0Gbps，實(shí)現(xiàn)了設(shè)計(jì)目標(biāo)。
[Abstract]:Packaging is an important part of the microprocessor, it used as a bridge connecting the chip with the outside world, it is very important for the performance of the whole system. With the development of integrated circuit technology, input and output interface of modern microprocessors with the rapid growth of the package shows the characteristics of high density packaging. The traditional design method gradually revealed the design difficulty increases, cannot meet the design requirements and design, has become a bottleneck restricting the development of microprocessor design.
This paper is based on "nuclear high base" major special high performance microprocessor project, aiming at the existing advanced microprocessor high density packaging design problems, research on collaborative design and simulation technology, studied multi stage coordination, signal and power integrity and collaborative design and Simulation of collaborative technology, including:
(1) multi stage package driven collaborative design planning. According to the traditional design method of chip package and circuit board, lack of independent design, this paper put forward the three as a whole collaborative design, and the center pin package for the uniform distribution of the system, to solve the unreasonable distribution of signal pins, go the line is not smooth, layout confusion and other issues.
(2) collaborative design. The signal and power supply layer planning based on interaction of the signal and the power of high density packaging in the increasingly serious, proposed in the laminated planning considering signal integrity and power integrity, collaborative design of signal and power, decreases in the package design of signal and power influence each other. The two is the best.
(3) the design and Simulation for package collaborative optimization. In order to solve the shortcomings of traditional design in the use of the principle of extensive design methods are proposed in this paper, combining with design and simulation, at the beginning of the design by simulation to develop accurate design rules and goals, verify the design by simulation in the design, to solve the lack of design and the design problem through the refinement method.
Based on the above method of collaborative design, this paper design a high density packaging advanced microprocessor. The processor mainly includes DDR3, PCIE, SATA and other 12 kinds of interface and 7 kinds of power supply, chip pin number reached 4733. by the method presented in this paper, the design and implementation of the processor chip package size is 42.5mm * 42.5mm and 1572 pin package a. Experimental results show that the chip can work stably in 1.2GHz, DDR, PCIE and SATA rate were respectively 1333Mbps, 5.0Gbps and 3.0Gbps, to achieve the design goals.

【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TP332;TN405

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