本文關(guān)鍵詞：數(shù)據(jù)驅(qū)動(dòng)異步微處理器設(shè)計(jì)關(guān)鍵技術(shù)研究　出處：《國防科學(xué)技術(shù)大學(xué)》2012年博士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： 異步電路 數(shù)據(jù)驅(qū)動(dòng) 微處理器 關(guān)鍵路徑分析 死鎖檢測(cè) 模擬評(píng)估 性能優(yōu)化 設(shè)計(jì)流程

【摘要】：隨著半導(dǎo)體工藝尺寸的不斷減小,單個(gè)芯片上可以集成的晶體管數(shù)目越來越多,同步電路設(shè)計(jì)遇到的時(shí)鐘偏差、功耗過大以及可靠性降低等問題也日益突出。異步電路使用本地握手信號(hào)來控制電路各模塊操作的時(shí)序,從根本上解決了同步電路設(shè)計(jì)面臨的問題。相對(duì)同步電路而言,異步電路具有功耗低、性能好、魯棒性高和電磁兼容性好等優(yōu)勢(shì)。因此,異步電路技術(shù)在未來微處理器發(fā)展過程中的應(yīng)用將越來越廣泛。目前,異步微處理器設(shè)計(jì)發(fā)展仍面臨諸多挑戰(zhàn),其中最主要是缺少相應(yīng)的CAD工具的支持。 本文針對(duì)數(shù)據(jù)驅(qū)動(dòng)異步微處理器設(shè)計(jì)與分析中的關(guān)鍵問題,對(duì)數(shù)據(jù)驅(qū)動(dòng)異步電路中的關(guān)鍵路徑分析、死鎖檢測(cè)、模擬評(píng)估、粗粒度數(shù)據(jù)驅(qū)動(dòng)異步電路設(shè)計(jì)流程等關(guān)鍵技術(shù)進(jìn)行了廣泛而深入的研究,并實(shí)現(xiàn)了數(shù)據(jù)驅(qū)動(dòng)異步微處理器原型,取得的主要研究成果包括： 1.提出了一種自動(dòng)化的數(shù)據(jù)驅(qū)動(dòng)異步電路關(guān)鍵路徑分析方法。基于數(shù)據(jù)驅(qū)動(dòng)異步電路設(shè)計(jì)工具Teak,利用異步電路模塊化特點(diǎn),在部件級(jí)和門級(jí)分別進(jìn)行分析,利用寬度優(yōu)先搜索算法將電路中的組合環(huán)路打開,然后采用多源最長(zhǎng)路徑算法分析出相鄰鎖存器之間的路徑長(zhǎng)度,根據(jù)關(guān)鍵路徑閥值來確定關(guān)鍵路徑。該分析方法可以在多項(xiàng)式時(shí)間內(nèi)對(duì)數(shù)據(jù)驅(qū)動(dòng)異步電路中的延遲分布情況進(jìn)行自動(dòng)化分析。在關(guān)鍵路徑分析基礎(chǔ)上實(shí)現(xiàn)了一種基于關(guān)鍵路徑的鎖存器插入方法,實(shí)驗(yàn)結(jié)果表明該鎖存器插入方法有效提高了電路的吞吐率 2.提出了一種基于結(jié)構(gòu)的數(shù)據(jù)驅(qū)動(dòng)異步電路死鎖檢測(cè)方法。針對(duì)傳統(tǒng)異步電路死鎖檢測(cè)方法面臨的狀態(tài)空間爆炸問題,本文通過分析電路的結(jié)構(gòu)特征,而非電路的狀態(tài)特征,給出無死鎖的良定義Steer-Merge-Fork-Join (SMFJ)部件網(wǎng)絡(luò)的結(jié)構(gòu)特征,并確定良定義SMFJ部件網(wǎng)絡(luò)的充要條件。同時(shí),本文分析了SMFJ部件網(wǎng)絡(luò)中通道的Slack彈性,為SMFJ部件網(wǎng)絡(luò)引入流水機(jī)制。最后,在數(shù)據(jù)驅(qū)動(dòng)異步電路設(shè)計(jì)工具Teak中實(shí)現(xiàn)了一種自動(dòng)化的死鎖檢測(cè)方法。實(shí)驗(yàn)結(jié)果表明,基于結(jié)構(gòu)的死鎖檢測(cè)方法與傳統(tǒng)的基于狀態(tài)空間的方法相比具有明顯的檢測(cè)效率優(yōu)勢(shì)。 3.提出了一種基于事件行為模型的數(shù)據(jù)驅(qū)動(dòng)異步電路模擬評(píng)估方法。對(duì)電路性能進(jìn)行驗(yàn)證評(píng)估最直接的途徑就是模擬,然而目前還沒有專門針對(duì)異步電路的模擬評(píng)估工具,設(shè)計(jì)者往往采用同步模擬工具對(duì)異步電路在設(shè)計(jì)后期進(jìn)行模擬,其時(shí)間開銷很大。本文針對(duì)數(shù)據(jù)驅(qū)動(dòng)異步電路提出事件行為模型,該模型構(gòu)造過程中包含有門級(jí)延遲信息�；谠撃Ｐ蛯�(shí)現(xiàn)了一款事件驅(qū)動(dòng)模擬器ESim用于對(duì)異步電路的模擬和性能評(píng)估。同時(shí),根據(jù)模擬過程中的執(zhí)行軌跡,實(shí)現(xiàn)了對(duì)異步電路性能的優(yōu)化。實(shí)驗(yàn)表明,ESim模擬器可以對(duì)電路性能進(jìn)行快速評(píng)估,并且在異步電路性能優(yōu)化方面具有很強(qiáng)的指導(dǎo)意義。 4.提出了一種粗粒度的數(shù)據(jù)驅(qū)動(dòng)異步電路設(shè)計(jì)流程。本文融合之前提出的關(guān)鍵路徑分析、死鎖檢測(cè)和模擬評(píng)估技術(shù),提出一套完整的粗粒度數(shù)據(jù)驅(qū)動(dòng)異步電路設(shè)計(jì)流程。與語法指導(dǎo)的異步電路設(shè)計(jì)流程不同,該流程基于基本數(shù)據(jù)驅(qū)動(dòng)部件,聚合數(shù)據(jù)處理部件,實(shí)現(xiàn)一種粗粒度的控制模式,簡(jiǎn)化了電路中的控制開銷,提高了電路性能。同時(shí),該流程與基于同步電路設(shè)計(jì)的流程不同,采用本文流程實(shí)現(xiàn)的異步電路不需要進(jìn)行延遲匹配,保持了異步電路的準(zhǔn)延遲無關(guān)特性,具有良好的魯棒性。 為了驗(yàn)證粗粒度數(shù)據(jù)驅(qū)動(dòng)異步電路設(shè)計(jì)流程及其關(guān)鍵支撐技術(shù)的可行性和有效性,本文基于該流程實(shí)現(xiàn)了一款安全異步微處理器原型NanoSpa,其中運(yùn)用了關(guān)鍵路徑分析技術(shù)、基于結(jié)構(gòu)的死鎖檢測(cè)技術(shù)以及基于事件行為模型的高層模擬評(píng)估技術(shù)等,實(shí)驗(yàn)結(jié)果表明使用粗粒度數(shù)據(jù)驅(qū)動(dòng)異步電路設(shè)計(jì)流程可以實(shí)現(xiàn)高效能的異步微處理器。
[Abstract]:With the decreasing size of semiconductor technology , the number of transistors that can be integrated on a single chip is more and more , and the problems such as clock deviation , excessive power consumption and lower reliability of synchronous circuit design are becoming more and more prominent . The asynchronous circuit has the advantages of low power consumption , good performance , high robustness and good electromagnetic compatibility . Aiming at the key problems in the design and analysis of data - driven asynchronous microprocessor , the key technologies such as key path analysis , deadlock detection , simulation evaluation , coarse - grained data - driven asynchronous circuit design flow in data - driven asynchronous circuits have been studied extensively , and the data - driven asynchronous microprocessor prototype has been realized . The main research results are as follows : 1 . An automatic data - driven asynchronous circuit - critical path analysis method is presented . Based on the data - driven asynchronous circuit design tool , the component - level and gate - level are analyzed by using the modularization feature of the asynchronous circuit . The path length between adjacent latches is analyzed by using a multi - source longest path algorithm . A key path - based latch insertion method is implemented based on the key path analysis . The experimental results show that the latch insertion method effectively improves the throughput rate of the circuit . 2 . A structure - based deadlock detection method for data - driven asynchronous circuits is presented . In this paper , the structural characteristics of the network of SMFJ parts are analyzed by analyzing the structural characteristics of the circuit and the state characteristics of the non - circuit . At the same time , the paper analyzes the Slack elasticity of the channel in the SMFJ component network and introduces a flow mechanism for SMFJ component networks . 3 . A data driven asynchronous circuit simulation evaluation method based on event behavior model is presented . The most direct way to evaluate the circuit performance is to simulate the asynchronous circuit . 4 . A coarse - grained data - driven asynchronous circuit design flow is put forward . The key path analysis , deadlock detection and simulation evaluation techniques presented before the integration of this paper propose a complete set of coarse - grained data - driven asynchronous circuit design flow , which is based on basic data - driven parts , aggregation data - processing parts , implements a coarse - grained control mode , simplifies the control overhead in the circuit and improves the circuit performance . In order to verify the feasibility and effectiveness of coarse - grained data - driven asynchronous circuit design flow and its key support technology , this paper implements a secure asynchronous microprocessor prototype NanoSpa based on this process , in which the key path analysis technology , structure - based deadlock detection technology and high - level simulation evaluation technology based on event behavior model are used . The experimental results show that the asynchronous circuit design flow can be driven by coarse - grained data to realize high - efficiency asynchronous microprocessor .

【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：博士
【學(xué)位授予年份】：2012
【分類號(hào)】：TP332

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