發(fā)布時間：2018-01-05 05:26

  本文關鍵詞：納米級下SRAM時序控制電路的魯棒性研究　出處：《安徽大學》2017年碩士論文　論文類型：學位論文

  更多相關文章： SRAM 靈敏放大器 復制位線 時序控制電路 標準偏差

【摘要】：隨著移動通信技術,3D技術,GPS導航技術,高速無線網絡技術的迅速發(fā)展,推動了現代集成電路設計追求更高的工藝水平。片上系統(tǒng)中嵌入式的Memory等存儲器已成為芯片設計的重要組成部分,預計到2017年片上Memory面積的百分比將達到90%以上。片上存儲器面積的增加、工藝偏差的增加以及電源電壓降低都使得片上存儲器的設計面臨巨大的挑戰(zhàn)。靜態(tài)隨機存儲器(Static Random Access Memory,簡稱:SRAM)因其高速、低功耗的特性被廣泛應用于手機,個人電腦等電子產品,因此,SRAM的性能將直接影響到SOC芯片的性能。晶體管閾值電壓(Vth)的工藝偏差將對SRAM的穩(wěn)定性和訪問時間造成很大的影響。針對這一問題,本文深入研究了工藝、電壓、溫度(簡稱:PVT)對于SRAM穩(wěn)定性的影響并提出了兩種更加有效的改進技術,主要內容如下:首先介紹了 SRAM主要的幾大結構,包括存儲陣列、靈敏放大器、譯碼器、讀寫控制電路等結構,并重點介紹了存儲陣列結構以及靈敏放大器的工作原理,然后分析了 SRAM讀操作的原理。接著介紹了兩種時序控制技術(反相器鏈延時技術和傳統(tǒng)復制位線技術),并對這兩種技術進行了對比,得出了復制位線技術更有優(yōu)勢的結論。接著介紹了近年來國內外的研究人員對SRAM時序控制電路進行的一些改進設計,重點介紹分析了其中的3種設計方案,分別是:數字復制位線技術、多級雙復制位線技術以及雙列交錯復制位線技術,對它們的結構和原理進行了深入分析,并做了一定的理論推導,并通過蒙特卡羅仿真與傳統(tǒng)復制位線技術進行了對比。最后,本文提出了兩種改進技術,第一種是雙列復制位線技術,第二種是基于自舉電路的復制位線技術,在以往的改進設計中,都是從復制位線結構本身來改進,而本文提出的第二種方案從復制位線的外圍電路中進行了改進,在不大量增加面積開銷的前提下,經仿真結果顯示,該方案取得了很好的改善效果。
[Abstract]:With the rapid development of mobile communication technology and GPS navigation technology, high-speed wireless network technology is developing rapidly. It promotes the modern IC design to pursue a higher level of technology. The embedded memory such as Memory in the on-chip system has become an important part of the chip design. It is expected that by 2017, the percentage of Memory area on the chip will be more than 90%. The area of on-chip memory will increase. The increase of process deviation and the decrease of power supply voltage make the design of on-chip memory face great challenge. Static Random Access Memory. Because of its high speed and low power consumption, it is widely used in electronic products such as mobile phones, personal computers and so on. The performance of SRAM will directly affect the performance of SOC chip. The process deviation of transistor threshold voltage will greatly affect the stability and access time of SRAM. In this paper, the effects of process, voltage and temperature on the stability of SRAM are studied and two more effective techniques are proposed. The main contents are as follows: firstly, several main structures of SRAM are introduced, including memory array, sensitive amplifier, decoder, read / write control circuit and so on. The structure of the memory array and the working principle of the sensitive amplifier are introduced in detail. Then the principle of SRAM read operation is analyzed, and then two kinds of timing control techniques (inverter chain delay technique and traditional copy bit line technique) are introduced, and the two techniques are compared. The conclusion that duplication bit line technology has more advantages is obtained. Then some improved designs of SRAM sequential control circuit are introduced by researchers at home and abroad in recent years. This paper mainly introduces and analyzes three design schemes, which are digital copy bit line technology, multilevel double copy bit line technology and double row interleaved replication bit line technology, and analyzes their structure and principle. Finally, this paper proposes two improved techniques, the first one is double-row replication bit line technology. The second is based on bootstrap circuit replication bit line technology, in the past improvement design, is from the replication bit line structure itself to improve. The second scheme proposed in this paper is improved from the peripheral circuit of the replica bit line. The simulation results show that the scheme has a good effect without increasing the area overhead.
【學位授予單位】：安徽大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TP333

【參考文獻】

相關期刊論文 前1條

1 Shou-biao TAN;Wen-juan LU;Chun-yu PENG;Zheng-ping LI;You-wu TAO;Jun-ning CHEN;;用于低電壓下SRAM靈敏放大器工藝變化魯棒性時序的多級雙復制位線延遲技術（英文）[J];Frontiers of Information Technology & Electronic Engineering;2015年08期

，

本文編號：1381762