本文關(guān)鍵詞：基于FPGA的高斯隨機(jī)數(shù)發(fā)生器的設(shè)計(jì)與實(shí)現(xiàn)　出處：《華南理工大學(xué)》2013年碩士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： 高斯隨機(jī)數(shù) Ziggurat高斯隨機(jī)數(shù)發(fā)生器 FPGA 冗余乘法器 Booth編碼

【摘要】：高斯隨機(jī)數(shù)在通信和雷達(dá)系統(tǒng)、航空航天、脈沖測(cè)距、蒙特卡羅模擬硬件加速器等領(lǐng)域獲得了廣泛應(yīng)用�，F(xiàn)有硬件實(shí)現(xiàn)的高斯隨機(jī)數(shù)發(fā)生器存在結(jié)構(gòu)復(fù)雜、設(shè)計(jì)周期長(zhǎng)等不足，本文對(duì)Ziggurat高斯隨機(jī)數(shù)發(fā)生器和定點(diǎn)乘法器進(jìn)行改進(jìn)，以減少硬件資源，提高工作頻率。完成的研究工作具體如下： 第一，本文提出的嵌套分割高斯隨機(jī)數(shù)發(fā)生器將高斯分布概率密度函數(shù)分為頂部、中部、尾部三個(gè)子區(qū)域，并分別進(jìn)行分層嵌套分割，有效提高了對(duì)概率密度函數(shù)的近似精度，輸出隨機(jī)數(shù)最大值從4.3提高到8.7。分割后以正比于矩形面積的概率隨機(jī)選擇一個(gè)矩形區(qū)域，生成概率密度函數(shù)為對(duì)應(yīng)矩形的隨機(jī)數(shù)點(diǎn)，其橫坐標(biāo)即為輸出的高斯隨機(jī)數(shù)。在此基礎(chǔ)上完成了改進(jìn)后隨機(jī)數(shù)發(fā)生器整體架構(gòu)、均勻分布隨機(jī)數(shù)發(fā)生器模塊、尾部區(qū)域模塊、頂部區(qū)域模塊等關(guān)鍵電路的設(shè)計(jì)和仿真。 第二，乘法器作為嵌套分割隨機(jī)數(shù)發(fā)生器中重要模塊，對(duì)隨機(jī)數(shù)發(fā)生器性能有著重要影響。本文基于Radix-16冗余Booth編碼，將奇數(shù)倍部分積改用冗余差分形式表示，改進(jìn)后需要計(jì)算的奇數(shù)倍被乘數(shù)從1個(gè)減少到0個(gè)。將改進(jìn)結(jié)構(gòu)推廣到Radix-32和Radix-64乘法器，奇數(shù)倍被乘數(shù)個(gè)數(shù)從3個(gè)和7個(gè)分別減少到1個(gè)，簡(jiǎn)化了控制信號(hào)產(chǎn)生電路和Booth解碼電路，減少了硬件資源使用和延時(shí)。 第三，本文對(duì)傳統(tǒng)部分積修正方法改進(jìn)，將修正位與部分積進(jìn)行壓縮，可將部分積數(shù)量從5個(gè)減少為4個(gè)。改進(jìn)后部分積低7位到達(dá)二進(jìn)制轉(zhuǎn)換電路時(shí)間更早，簡(jiǎn)化了二進(jìn)制轉(zhuǎn)換電路結(jié)構(gòu)，降低了乘法器延時(shí)和面積。TSMC180nm工藝下Design Complier綜合結(jié)果表明，本文改進(jìn)乘法器相對(duì)傳統(tǒng)冗余乘法器面積減少8%，延時(shí)減少11%。 最后，在FPGA上對(duì)改進(jìn)的隨機(jī)數(shù)發(fā)生器綜合，相比Ziggurat隨機(jī)數(shù)發(fā)生器硬件資源減少9.0%、速度提升8.2%；統(tǒng)計(jì)檢驗(yàn)表明生成的隨機(jī)數(shù)服從高斯分布；將本文隨機(jī)數(shù)發(fā)生器應(yīng)用于蒙特卡羅模擬FPGA硬件加速器中，驗(yàn)證了隨機(jī)數(shù)發(fā)生器的有效性。 綜上所述，本文提出的嵌套分割隨機(jī)數(shù)發(fā)生器和改進(jìn)乘法器可有效減少硬件資源，提高隨機(jī)數(shù)發(fā)生器吞吐率，，達(dá)到了設(shè)計(jì)目標(biāo)。
[Abstract]:The Gauss random number in communication and radar systems, aerospace, pulse ranging, Monte Carlo simulation hardware accelerator is widely used. The Gauss random number generator existing hardware implementation has complicated structure, long design period, this paper improves Ziggurat Gauss random number generator and the fixed-point multiplier, in order to reduce the hardware resources, improve the working frequency of the completion of the research work as follows:
First, the proposed nested segmentation Gauss random number generator Gauss distribution probability density function is divided into top, middle and tail of three sub regions, which were hierarchical nested segmentation, effectively improve the approximation accuracy of the probability density function of the random number, output the maximum value increased from 4.3 to 8.7. after the split in proportion to the random selection of rectangular the area of the probability of a rectangular area, generating probability density function of random points corresponding to rectangular, the abscissa is the Gauss random number output. Based on the improved random number generator overall structure, uniform random number generator module, rear area module, design and Simulation of the key circuit module area at the top..
Second, as an important module multiplier nested partition random number generator, and has an important influence on the performance of the random number generator. The Radix-16 redundant Booth encoding based on the odd times of partial product with redundant differential form, the improved calculation need odd times the multiplicand is reduced from 1 to 0. The improved structure is extended to Radix-32 and the Radix-64 multiplier, the number of odd times of the multiplicand from 3 and 7 respectively reduced to 1, simplifies the control signal generating circuit and a Booth decoding circuit, reducing the use of hardware resources and time delay.
Third, improve the traditional correction method of partial product, and will correct the partial product compression, the number of partial products reduced from 5 to 4. The improved partial product low 7 bit binary conversion circuit at earlier time, simplified binary conversion circuit structure, reduced by Design Complier adder delay and comprehensive results the area under the.TSMC180nm technology show that the improved multiplier multiplier area decreased by 8% compared with the traditional redundancy, reduce the delay of 11%.
Finally, the random number generator comprehensive improvement in FPGA, compared with Ziggurat random number generator hardware resource is reduced by 9%, speed increased by 8.2%; the statistical tests show that the generated random number obeys Gauss distribution; the application of random number generator in Monte Carlo simulation of FPGA hardware accelerator, to verify the effectiveness of the random number generator.
To sum up, the nested split random number generator and improved multiplier proposed in this paper can effectively reduce hardware resources and improve the throughput of random number generator, and achieve the design goal.

【學(xué)位授予單位】：華南理工大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP346;TN791

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