發(fā)布時(shí)間：2018-01-03 03:01

  本文關(guān)鍵詞：基于基地址寄存器映射的數(shù)據(jù)高速緩存設(shè)計(jì)研究　出處：《浙江大學(xué)》2013年碩士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： 數(shù)據(jù)高速緩存 低功耗技術(shù) 基地址寄存器映射 數(shù)據(jù)緩存 零級(jí)數(shù)據(jù)高速緩存 索引跟蹤技術(shù)

【摘要】：高速緩存作為內(nèi)存與處理器之間的橋梁,其性能與功耗問題日益受到關(guān)注。本文圍繞高速緩存的低功耗技術(shù),研究了存儲(chǔ)器訪問特性和零級(jí)數(shù)據(jù)高速緩存相關(guān)技術(shù),為本文設(shè)計(jì)提供理論依據(jù)。本文的主要內(nèi)容及創(chuàng)新點(diǎn)包括： 1.提出一種適用于嵌入式處理器的基于基地址寄存器映射的數(shù)據(jù)緩存訪問方法。該方法的核心思想是在加載指令執(zhí)行過程中動(dòng)態(tài)構(gòu)建基地址寄存器與目標(biāo)數(shù)據(jù)的局部性訪問歷史,并通過設(shè)計(jì)基地址寄存器跟蹤緩存器在指令譯碼后直接獲得目標(biāo)數(shù)據(jù),從而加速加載指令的數(shù)據(jù)獲取過程,減少地址計(jì)算和對(duì)高速緩存的訪問。測(cè)試基準(zhǔn)的運(yùn)行結(jié)果顯示,基于本方法的處理器性能提高平均約3.7%,數(shù)據(jù)高速緩存功耗降低平均約16.6%。 2.提出一種既能降低高速緩存訪問功耗,又能提升處理器性能的零級(jí)數(shù)據(jù)高速緩存結(jié)構(gòu)。該結(jié)構(gòu)基于基地址寄存器映射,利用索引跟蹤技術(shù),通過在譯碼級(jí)加入索引跟蹤器,在裝載/存儲(chǔ)單元加入地址檢查表,來達(dá)到減少裝載指令訪問延時(shí)與降低訪問功耗的目的。測(cè)試基準(zhǔn)的運(yùn)行結(jié)果顯示,基于基地址寄存器映射的零級(jí)數(shù)據(jù)高速緩存能使數(shù)據(jù)高速緩存功耗降低平均約28%,處理器性能提升平均約3.5%,與常規(guī)零級(jí)數(shù)據(jù)高速緩存相比,處理器性能提升平均約7.4%,功耗降低作用相同。
[Abstract]:Cache, as a bridge between memory and processor, has attracted more and more attention on its performance and power consumption. This paper focuses on the low-power technology of cache. The memory access characteristics and zero-level data cache technologies are studied, which provide a theoretical basis for the design of this paper. The main contents and innovations of this paper are as follows: 1. A data cache access method based on base address register mapping is proposed for embedded processor. The key idea of this method is to dynamically construct the base address register and the target number during the execution of the instruction. According to the local visit history. By designing the base address register tracking buffer, the target data can be obtained directly after the instruction decoding, thus speeding up the data acquisition process of the loading instruction. The test results show that the performance of the processor based on this method is improved by about 3.7 on average, and the power consumption of data cache is reduced by about 16.6. 2. A zero-level data cache architecture, which can reduce cache access power consumption and improve processor performance, is proposed, which is based on base address register mapping and uses index tracking technology. By adding an index tracker at the decoding level and adding an address check table to the load / memory unit, the purpose of reducing the load instruction access delay and the access power consumption is achieved. The running results of the test benchmark are shown. The zero-level data cache based on base address register mapping can reduce the average power consumption of the data cache by about 28%, and improve the processor performance by an average of about 3.5%, compared with the conventional zero level data cache. The average processor performance improvement is about 7.4, and the power reduction function is the same.
【學(xué)位授予單位】：浙江大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP333

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本文編號(hào)：1372070