發(fā)布時(shí)間：2018-01-02 17:34

  本文關(guān)鍵詞：閃存的關(guān)鍵電路設(shè)計(jì)與優(yōu)化　出處：《山東大學(xué)》2014年碩士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： NOR FLASH 操作算法 外圍電路 讀通路

【摘要】：近年來(lái),快速閃存憑借優(yōu)異的性能,在電子信息領(lǐng)域得到了廣泛應(yīng)用。隨著信息社會(huì)的發(fā)展,信息產(chǎn)業(yè)正朝著海量信息計(jì)算、存儲(chǔ)、傳輸?shù)姆较虬l(fā)展。這就要求快速閃存存儲(chǔ)技術(shù)向大規(guī)模、高速度、低功耗、低成本發(fā)展。 浮柵型存儲(chǔ)器的設(shè)計(jì),隨著工藝特征尺寸的減小而面臨著挑戰(zhàn)。首先,低供電電壓增加了設(shè)計(jì)難度；第二,隨著存儲(chǔ)容量的增大,讀通路寄生效應(yīng)更加顯著；第三,工藝漲落在所難免。這些問(wèn)題都與存儲(chǔ)器外圍電路和讀通路的設(shè)計(jì)密切相關(guān)。因此,本文首先深入研究了NOR FLASH工作原理,重點(diǎn)設(shè)計(jì)了NOR FLASH外圍電路,對(duì)讀通路進(jìn)行設(shè)計(jì)、優(yōu)化,并設(shè)計(jì)了利用預(yù)設(shè)Trim值對(duì)抗工藝漲落的方法。本文的主要工作和成果如下： 1.深入研究了浮柵晶體管的工作原理,對(duì)NOR FLASH的編程、擦除算法進(jìn)行了詳細(xì)闡述。 2.設(shè)計(jì)了幾種外圍關(guān)鍵電路,包括：(1)兩款基準(zhǔn)電壓源,一款是曲率補(bǔ)償?shù)母呔然鶞?zhǔn)電壓源,另一款是抗工藝漲落的待機(jī)狀態(tài)下的基準(zhǔn)電壓源；(2)一種瞬態(tài)響應(yīng)增強(qiáng)型VDC電路；(3)改進(jìn)型電平轉(zhuǎn)換電路。 3.設(shè)計(jì)優(yōu)化了讀通路關(guān)鍵電路,包括：(1)一種新型的參考電流源電路；(2)電流轉(zhuǎn)電壓電路；(3)改進(jìn)型靈敏放大器。 4.考慮讀通路的寄生效應(yīng),優(yōu)化讀通路。 5.為了削弱工藝漲落對(duì)系統(tǒng)的影響,設(shè)計(jì)了Trim值讀取電路。
[Abstract]:In recent years , the rapid flash memory has been widely used in the field of electronic information . With the development of information society , the information industry is developing in the direction of mass information calculation , storage and transmission . This requires fast flash memory technology to develop in large scale , high speed , low power consumption and low cost . The design of floating gate type memory faces the challenge with the decrease of process feature size . First , the low supply voltage increases the design difficulty ; secondly , with the increase of storage capacity , the parasitic effect of read path is more significant ; thirdly , the process fluctuation is inevitable . Therefore , this paper studies the NOR FLASH working principle , designs and optimizes the read path , and designs the method of using the preset Trim value to counter the process fluctuation . The main work and results of this paper are as follows : 1 . The working principle of floating gate transistor is researched deeply , and the programming and erase algorithm of NOR FLASH is explained in detail . 2 . Several peripheral key circuits are designed , including : ( 1 ) two reference voltage sources , one is the high - precision reference voltage source with curvature compensation , the other is the reference voltage source in the standby state of the anti - process fluctuation ; ( 2 ) the transient response enhanced VDC circuit ; and ( 3 ) the improved level conversion circuit . 3 . The key circuit of read path is optimized , including : ( 1 ) a new reference current source circuit ; ( 2 ) current - to - voltage circuit ; ( 3 ) improved sense amplifier . 4 . Considering the parasitic effect of the read path , the read path is optimized . 5 . Trim value reading circuit is designed to weaken the effect of process fluctuation .

【學(xué)位授予單位】：山東大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TP333

【參考文獻(xiàn)】

相關(guān)博士學(xué)位論文 前1條

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本文編號(hào)：1370239