真空定向凝固去除硅中揮發(fā)性雜質及其應用研究
發(fā)布時間：2018-08-02 20:14
【摘要】：多晶硅是光伏發(fā)電的基本材料,物理冶金法因其成本低、工藝簡單、設備投資少等優(yōu)勢將逐步取代西門子法成為多晶硅材料生產的主要技術。作為冶金法工藝流程中的核心技術——真空定向凝固可以實現(xiàn)多晶硅的提純與鑄錠。然而,真空定向凝固一些關鍵技術還沒有突破,導致其制備多晶硅的潛力并沒有充分發(fā)揮。本文基于真空表面揮發(fā)和定向凝固分凝原理,進行了真空定向凝固去除硅中揮發(fā)性雜質的動力學研究,推導并驗證了一個適合工業(yè)化真空定向凝固去除硅中揮發(fā)性雜質的數(shù)學模型。通過計算探討了熔煉溫度、固-液相邊界層厚度和凝固速率對揮發(fā)性雜質有效分凝系數(shù)的影響。結果表明,熔煉溫度上升或固-液邊界層厚度變薄可導致硅中揮發(fā)性雜質的有效分凝系數(shù)變小,但幅度不大,且其減小趨勢逐步放緩。凝固速率的降低導致雜質的有效分凝系數(shù)降低,且這種影響決定了揮發(fā)性雜質的分凝效果。結合多晶硅鑄錠爐特點,本文選取了隔熱板下拉速率作為多晶硅鑄錠爐提純多晶硅工藝改進的對象。通過不同高度下的雜質分布,反推出硅錠高度與有效分凝系數(shù)直接的關系。將其對應于理想狀態(tài)下的有效分凝系數(shù)公式,得到了最佳有效分凝系數(shù)時凝固速率與硅錠凝固時間之間的關系�？紤]到雜質去除和晶體生長兩種因素,研究獲得了鑄錠爐提純和鑄錠提純兼顧鑄錠提純兩套工藝。本文分別采用電感耦合等離子體發(fā)射光譜儀(ICP-AES)、WT2000面掃描少子壽命測試儀、四探針測電阻法分別對兩套工藝產出硅錠樣品的雜質含量、少子壽命、電阻率進行檢測。結果表明,提純工藝產出硅錠中,雜質銅的含量均低于0.5ppmw,雜質磷的含量低于3ppmw,其他金屬雜質均低于檢測值。樣品的少子壽命平均值在0.61μs到0.75μs范圍內。中部樣品的電阻率在0.2 Ω·cm～0.6 Ω·cm范圍之內,硅錠邊部樣品的電阻率在0.15 Ω·cm-0.5 Ω-·cm范圍之內；提純兼顧工藝產出硅錠中,雜質鐵和鈦的含量均低于儀器的檢測值,其余硅中金屬雜質含量基本低于lppmw。少子壽命的平均值在5.851μs到6.466μs之間。中部樣品的電阻率在0.25 Ω·cm-0.45Ω.cm范圍之內,邊部樣品的電阻率在0.15 Ω·cm～0.5 Ω·cm范圍之內。此外,根據(jù)雜質分布公式計算了硅錠成品的切割位置。根據(jù)計算位置切割硅錠相比原有切割位置直接提高硅錠收得率3.5～4%,單爐(500kg)提高產量15-20kg。
[Abstract]:Polycrystalline silicon is the basic material for photovoltaic power generation. Because of its advantages of low cost, simple process and less equipment investment, polycrystalline silicon process will gradually replace Siemens process as the main technology of polysilicon material production. As the core technology of metallurgical process, vacuum directional solidification can realize the purification and ingot of polysilicon. However, some key technologies of vacuum directional solidification have not been broken through, and the potential of preparing polysilicon has not been fully realized. Based on the principle of vacuum surface volatilization and directional solidification separation, the kinetics of removing volatile impurities from silicon by vacuum directional solidification has been studied in this paper. A mathematical model for the removal of volatile impurities in silicon by industrial vacuum directional solidification was derived and verified. The effects of melting temperature, solid-liquid boundary layer thickness and solidification rate on the effective segregation coefficient of volatile impurities were investigated. The results show that the increase of melting temperature or the thickness of solid-liquid boundary layer can result in the decrease of effective segregation coefficient of volatile impurities in silicon, but the decrease trend is slowing down gradually. The decrease of solidification rate leads to the decrease of effective segregation coefficient of impurity, and this effect determines the coagulating effect of volatile impurity. According to the characteristics of polycrystalline silicon ingot furnace, this paper selects the pull-down rate of heat insulation board as the object of improving the process of purification of polysilicon ingot furnace. Through the impurity distribution at different heights, the direct relationship between the silicon ingot height and the effective segregation coefficient is deduced. The relationship between the solidification rate and the solidification time of silicon ingot is obtained by using the formula of effective segregation coefficient corresponding to the ideal state. Considering the two factors of impurity removal and crystal growth, two processes of ingot purification and ingot purification were obtained. In this paper, the impurity content, minority carrier lifetime and resistivity of silicon ingot samples produced by two sets of processes were measured by inductively coupled plasma emission spectrometer (ICP-AES) and WT2000 scanning minority carrier lifetime tester and four-probe resistance method respectively. The results show that the content of impurity copper is lower than 0.5ppmw. the content of impurity phosphorus is lower than 3ppmw. the other metal impurity is lower than the detection value. The average minority carrier lifetime of the sample ranges from 0.61 渭 s to 0.75 渭 s. The resistivity of the middle sample is within the range of 0. 2 惟 cm~0.6 惟 cm, the resistivity of the sample at the edge of the silicon ingot is within 0. 15 惟 cm-0.5 惟-cm, and the content of impurity iron and titanium in the silicon ingot produced by the purification process is lower than the measured value of the instrument. The content of metal impurity in other silicon is lower than that in lppmw. The average minority carrier lifetime ranges from 5.851 渭 s to 6.466 渭 s. The resistivity of the middle sample is within the range of 0.25 惟 cm-0.45 惟 路cm, and the resistivity of the edge sample is within the range of 0.15 惟 cm~0.5 惟 cm. In addition, the cutting position of the finished silicon ingot was calculated according to the impurity distribution formula. According to the calculated position, the yield of silicon ingot is directly increased by 3.5 ~ 4% compared with the original cutting position, and the output of single furnace (500kg) is increased by 15-20 kg.
【學位授予單位】：昆明理工大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TQ127.2
本文編號：2160598
[Abstract]:Polycrystalline silicon is the basic material for photovoltaic power generation. Because of its advantages of low cost, simple process and less equipment investment, polycrystalline silicon process will gradually replace Siemens process as the main technology of polysilicon material production. As the core technology of metallurgical process, vacuum directional solidification can realize the purification and ingot of polysilicon. However, some key technologies of vacuum directional solidification have not been broken through, and the potential of preparing polysilicon has not been fully realized. Based on the principle of vacuum surface volatilization and directional solidification separation, the kinetics of removing volatile impurities from silicon by vacuum directional solidification has been studied in this paper. A mathematical model for the removal of volatile impurities in silicon by industrial vacuum directional solidification was derived and verified. The effects of melting temperature, solid-liquid boundary layer thickness and solidification rate on the effective segregation coefficient of volatile impurities were investigated. The results show that the increase of melting temperature or the thickness of solid-liquid boundary layer can result in the decrease of effective segregation coefficient of volatile impurities in silicon, but the decrease trend is slowing down gradually. The decrease of solidification rate leads to the decrease of effective segregation coefficient of impurity, and this effect determines the coagulating effect of volatile impurity. According to the characteristics of polycrystalline silicon ingot furnace, this paper selects the pull-down rate of heat insulation board as the object of improving the process of purification of polysilicon ingot furnace. Through the impurity distribution at different heights, the direct relationship between the silicon ingot height and the effective segregation coefficient is deduced. The relationship between the solidification rate and the solidification time of silicon ingot is obtained by using the formula of effective segregation coefficient corresponding to the ideal state. Considering the two factors of impurity removal and crystal growth, two processes of ingot purification and ingot purification were obtained. In this paper, the impurity content, minority carrier lifetime and resistivity of silicon ingot samples produced by two sets of processes were measured by inductively coupled plasma emission spectrometer (ICP-AES) and WT2000 scanning minority carrier lifetime tester and four-probe resistance method respectively. The results show that the content of impurity copper is lower than 0.5ppmw. the content of impurity phosphorus is lower than 3ppmw. the other metal impurity is lower than the detection value. The average minority carrier lifetime of the sample ranges from 0.61 渭 s to 0.75 渭 s. The resistivity of the middle sample is within the range of 0. 2 惟 cm~0.6 惟 cm, the resistivity of the sample at the edge of the silicon ingot is within 0. 15 惟 cm-0.5 惟-cm, and the content of impurity iron and titanium in the silicon ingot produced by the purification process is lower than the measured value of the instrument. The content of metal impurity in other silicon is lower than that in lppmw. The average minority carrier lifetime ranges from 5.851 渭 s to 6.466 渭 s. The resistivity of the middle sample is within the range of 0.25 惟 cm-0.45 惟 路cm, and the resistivity of the edge sample is within the range of 0.15 惟 cm~0.5 惟 cm. In addition, the cutting position of the finished silicon ingot was calculated according to the impurity distribution formula. According to the calculated position, the yield of silicon ingot is directly increased by 3.5 ~ 4% compared with the original cutting position, and the output of single furnace (500kg) is increased by 15-20 kg.
【學位授予單位】：昆明理工大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TQ127.2
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