本文選題：FPGA + ARM��； 參考：《中國科學(xué)技術(shù)大學(xué)》2016年碩士論文

【摘要】：隨著地球物理勘探技術(shù)的不斷發(fā)展,探測設(shè)備的器件正向著更高精度的ADC、處理能力更強(qiáng)的CPU、以及更加先進(jìn)的傳感器的方向升級(jí)換代,以采集到更高保真、更豐富、更清晰的地震數(shù)據(jù)。然而當(dāng)前采集設(shè)備體積龐大,在探測大范圍地理區(qū)域時(shí),傳輸電纜長度受到距離的限制、不能實(shí)時(shí)處理和保存數(shù)據(jù)、時(shí)鐘同步難度大。本文提出一種分布式探測方案,利用GPS的精準(zhǔn)授時(shí)信號(hào)同步各節(jié)點(diǎn)設(shè)備的時(shí)鐘,構(gòu)成一個(gè)探測網(wǎng)絡(luò)。把GPS、ARM、FPGA、ADC集成到一個(gè)板子上,組成一個(gè)獨(dú)立的探測節(jié)點(diǎn),縮小了設(shè)備體積以便攜帶。節(jié)點(diǎn)設(shè)備使用內(nèi)部電源供電以脫離電纜長度的限制,同時(shí)使用強(qiáng)大的CPU對(duì)數(shù)據(jù)進(jìn)行實(shí)時(shí)處理并存儲(chǔ)在內(nèi)部存儲(chǔ)器中。本論文共分為六個(gè)部分：第一章簡單介紹了當(dāng)前地球物理采集設(shè)備現(xiàn)狀以及發(fā)展趨勢,接著研究了GPS精準(zhǔn)授時(shí)在地球物理探測中的應(yīng)用及相關(guān)的技術(shù)。第二章主要介紹了地球物理節(jié)點(diǎn)設(shè)備的總體設(shè)計(jì)結(jié)構(gòu),包括硬件電路的數(shù)據(jù)傳輸流程設(shè)計(jì)、硬件電路的PCB元件布置方案,FPGA部分采集數(shù)據(jù)以及數(shù)據(jù)封包邏輯總體設(shè)計(jì),ARM部分采集數(shù)據(jù)解析與同步時(shí)鐘對(duì)齊分析程序總體設(shè)計(jì)。第三章詳細(xì)介紹了地球物理節(jié)點(diǎn)設(shè)備硬件電路的設(shè)計(jì),包括電源部分的供電電源設(shè)計(jì)與器件選型,數(shù)據(jù)采集處理的詳細(xì)電路設(shè)計(jì)與相關(guān)器件介紹,數(shù)據(jù)存儲(chǔ)分析電路的詳細(xì)設(shè)計(jì)與相關(guān)器件介紹,接著介紹了本論文設(shè)計(jì)采用的ADC采集芯片,最后介紹了模擬信號(hào)源的相關(guān)設(shè)計(jì)第四章首先從FPGA的硬件描述語言(verilog)進(jìn)行介紹同時(shí)講述了FPGA的仿真工具與開發(fā)環(huán)境,接著介紹了ADC控制器的邏輯設(shè)計(jì),GPS數(shù)據(jù)采集的邏輯設(shè)計(jì)與GPS的授時(shí)信號(hào)及數(shù)據(jù)匯總模塊的邏輯設(shè)計(jì),最后介紹了雙RAM乒乓操作的邏輯設(shè)計(jì)。第五章介紹了linux嵌入式系統(tǒng)的相關(guān)背景以及針對(duì)本論文所設(shè)計(jì)系統(tǒng)編譯Uboot、內(nèi)核kernel與linux文件系統(tǒng),隨后介紹了根據(jù)FPGA與ARM進(jìn)行通訊所必要的數(shù)據(jù)采集接口設(shè)計(jì),以及采集到的原始數(shù)據(jù)文件的轉(zhuǎn)換與轉(zhuǎn)換之后的數(shù)據(jù)基于GPS授時(shí)信號(hào)的合并處理,最后介紹系統(tǒng)測試所用的模擬信號(hào)源的程序設(shè)計(jì)。第六章主要對(duì)本文設(shè)計(jì)的實(shí)際電路進(jìn)行設(shè)備性能的測試,對(duì)采集到數(shù)據(jù)進(jìn)行分析是否可以滿足要求,同時(shí)測試多節(jié)點(diǎn)時(shí)所采集到的數(shù)據(jù)在PPS信號(hào)的對(duì)齊校準(zhǔn)下是否數(shù)據(jù)同步,最后對(duì)本文所做的工作做總結(jié)以及對(duì)未來工作的展望。
[Abstract]:With the continuous development of geophysical exploration technology, the devices of detection equipment are being upgraded to higher precision ADCs, more powerful CPU, and more advanced sensors, in order to acquire higher fidelity and richer. Clearer seismic data. However, because of the large volume of the current acquisition equipment, the length of transmission cable is limited by the distance, and the data can not be processed and saved in real time, so it is difficult to synchronize the clock. In this paper, a distributed detection scheme is proposed to synchronize the clocks of each node by using the precise timing signal of GPS to form a detection network. The GPS-ARM FPGA ADC is integrated into a single board to form an independent probe node, which reduces the size of the device for carrying. Node devices use internal power to supply power away from cable length constraints, and use powerful CPU to process data in real time and store it in internal memory. This paper is divided into six parts: the first chapter briefly introduces the current situation and development trend of geophysical acquisition equipment, and then studies the application of GPS precise timing in geophysical detection and related technology. The second chapter mainly introduces the overall design structure of geophysical node equipment, including the design of hardware circuit data transmission flow. The overall Design of data acquisition and data packet Logic in PCB part of hardware Circuit the whole program of data analysis and synchronous clock alignment for arm part is designed. The third chapter introduces the design of the hardware circuit of geophysical node equipment in detail, including the power supply design and device selection of power supply, the detailed circuit design of data acquisition and processing and the introduction of related devices. The detailed design of the data storage and analysis circuit and the related devices are introduced. Then, the ADC acquisition chip used in this paper is introduced. Finally, the related design of analog signal source is introduced in Chapter 4. Firstly, the hardware description language of FPGA is introduced, and the simulation tools and development environment of FPGA are also described. Then the logic design of ADC controller and the logic design of GPS timing signal and data summary module are introduced. Finally, the logic design of double RAM ping-pong operation is introduced. Chapter five introduces the background of linux embedded system and the design of data acquisition interface which is necessary for the communication between FPGA and ARM by compiling UbootUp, kernel kernel and linux file system for the system designed in this paper. The conversion of the original data file and the data after the conversion are based on the combined processing of the GPS timing signal. Finally, the program design of the analog signal source used in the system test is introduced. The sixth chapter mainly tests the equipment performance of the actual circuit designed in this paper, analyzes whether the collected data can meet the requirements, and tests whether the data collected when the multi-node is calibrated under the alignment of PPS signal, whether the data is synchronized or not. Finally, the work done in this paper is summarized and the future work is prospected.
【學(xué)位授予單位】：中國科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2016
【分類號(hào)】：P631.4;TN791

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