A 10Gb/s 6-tap transmit equalizer based on partial response signaling for high speed backplane transmission is presented. By combining features of equalizer and frequency-dependent channel,duobinary signaling can be generated at the output of FR4 backplane,aiming at increasing data rate while reducing design complexity. Based on 0.18μm CMOS technology,this equalizer has been designed and fabricated,in which both variable capacitor and load resistor calibration techniques are explored to eliminat... 

【文章來源】：High Technology Letters. 2017,23(03)EI

【文章頁(yè)數(shù)】：5 頁(yè)

【文章目錄】：
0 Introduction
1 Architecture design
2 Circuit design
    2.1 Delay unit
    2.2 Delay line optimization using calibration tech-niques
    2.3 Multiplier-summer
3 Experimental results
4 Conclusion



本文編號(hào)：3236047