【摘要】：本文通過分析平面結(jié)構(gòu)硅磁敏三極管基本結(jié)構(gòu)、工作原理和特性,給出集成化SOI硅磁敏三極管差分結(jié)構(gòu),該集成化結(jié)構(gòu)由兩個具有相反磁敏感方向的SOI硅磁敏三極管(PSMST1、PSMST2)和集電極負(fù)載電阻(RL1、RL2)構(gòu)成,包括一個發(fā)射極(E)、兩個基極(B1、B2)、兩個集電極(C1、C2)和兩個集電極負(fù)載電阻。根據(jù)基本結(jié)構(gòu),采用ATLAS軟件構(gòu)建平面硅磁敏三極管仿真模型,研究基區(qū)長度(L)、基區(qū)寬度(w)、發(fā)射區(qū)寬度(WE)和襯底類型對其IC-VCE特性、磁特性和溫度特性的影響,實現(xiàn)結(jié)構(gòu)參數(shù)優(yōu)化,在此基礎(chǔ)上,構(gòu)建SOI硅磁敏三極管差分結(jié)構(gòu)仿真模型進(jìn)行仿真分析�；谏鲜�,本文在器件層為100晶向P型高阻(ρ1000?·cm)SOI片上研究、設(shè)計并制作集成化SOI硅磁敏三極管差分結(jié)構(gòu)。通過使用半導(dǎo)體參數(shù)測試儀(Keithley 4200)、磁場發(fā)生器系統(tǒng)(CH-100)、萬用表(Agilent 34401A)、恒流源(Rigol SD120)、恒壓源(Rigol DP832)以及高低溫試驗箱(Obis GDJS-100LG-G)等實驗儀器,對不同幾何結(jié)構(gòu)尺寸的集成化SOI硅磁敏三極管差分結(jié)構(gòu)芯片進(jìn)行IC-VCE特性、磁特性和溫度特性測試。根據(jù)實驗結(jié)果,選出本文最優(yōu)幾何結(jié)構(gòu)尺寸,即WE、w和L分別為400μm、50μm和100μm,當(dāng)VDD=3.5 V,IB=0.5 mA時,SOI硅磁敏三極管和SOI硅磁敏三極管差分結(jié)構(gòu)集成化芯片的集電極電壓輸出絕對磁靈敏度分別為68.97 mV/T和132.72 mV/T,集電極電壓輸出相對溫度系數(shù)分別為548 ppm/℃和376 ppm/℃。實驗結(jié)果表明,SOI硅磁敏三極管差分結(jié)構(gòu)集成化芯片可以提高磁靈敏度、改善溫度特性。
[Abstract]:Based on the analysis of the basic structure, working principle and characteristics of the planar structure silicon magnetosensitive transistor, the differential structure of the integrated SOI silicon-sensitive triode is given. The integrated structure is composed of two SOI silicon-sensitive transistors (PSMST1, PSMST2) and a collector load resistor (RL1, RL2) comprising an emitter (E), two base (B1, B2), two collectors (C1, C2) and two collector load resistors. according to the basic structure, an ATLAS software is adopted to construct a planar silicon magnetosensitive triode simulation model, the influence of the base length (L), the base width (w), the emission region width (WE) and the substrate type on the IC-VCE characteristic, the magnetic property and the temperature characteristic is studied, and the structural parameter optimization is realized, On this basis, the simulation model of the differential structure of SOI silicon-sensitive triode is constructed. Based on the above, in the device layer, the device layer is 100 crystal-to-P type high-resistance (F1000). 路 cm) On-chip research, design and fabrication of integrated SOI silicon-sensitive triode differential structure. By using a semiconductor parameter tester (Keithley 4200), a magnetic field generator system (CH-100), a multimeter (Agilent 34401A), a constant current source (Rigl SD120), a constant voltage source (Rigl DP832), and a high and low temperature test chamber (Obis GDJS-100LG-G), The IC-VCE characteristic, the magnetic property and the temperature characteristic test are carried out on the integrated SOI silicon-sensitive triode differential structure chip with different geometric structure sizes. According to the experimental results, the optimal geometric structure dimensions, WE, w and L are 400. m u.m,50. m and 100. m u.m, respectively, and when VDD = 3.5 V, IB = 0.5 mA, The absolute magnetic sensitivity of the collector voltage of the integrated chip is 68.97 mV/ T and 132.72 mV/ T, respectively, and the relative temperature coefficient of the collector voltage is 548 ppm/ 鈩，

本文編號：2508602