基于SMIC 65nm工藝的靜態(tài)隨機(jī)存儲(chǔ)芯片的后端設(shè)計(jì)
發(fā)布時(shí)間：2019-06-26 12:45
【摘要】：隨著移動(dòng)互聯(lián)網(wǎng)技術(shù)的發(fā)展,片上系統(tǒng)的速度不斷提高,推動(dòng)了高速緩存對(duì)速度的需求。作為高速緩存的核心部件,靜態(tài)隨機(jī)存儲(chǔ)器便成為了系統(tǒng)速度提升和功耗降低的關(guān)鍵。而且集成電路芯片的更新速度逐步加快,工程師們迫切希望縮短從最初設(shè)計(jì)到最終進(jìn)入市場(chǎng)的時(shí)間,傳統(tǒng)的基于管級(jí)的全定制設(shè)計(jì)方法就不能滿足這一需求,而基于門級(jí)的半定制設(shè)計(jì)方法便成為集成電路設(shè)計(jì)領(lǐng)域中的主流。在半定制設(shè)計(jì)中最重要的革新環(huán)節(jié)就是后端設(shè)計(jì),并且該項(xiàng)工作已成為各個(gè)公司和研究所的重點(diǎn)研究課題。集成電路的技術(shù)水平已經(jīng)進(jìn)入到深亞微米階段,工程師在其后端設(shè)計(jì)領(lǐng)域中逐漸面臨著越來(lái)越多的問(wèn)題和越來(lái)越嚴(yán)重的挑戰(zhàn)。例如,芯片特征尺寸的逐漸縮小導(dǎo)致互連效應(yīng)問(wèn)題的出現(xiàn);芯片規(guī)模的不斷增大導(dǎo)致運(yùn)行時(shí)間急劇膨脹,極大影響了設(shè)計(jì)流程的迭代效率;信號(hào)完整性分析成為一項(xiàng)必需工作,給芯片的時(shí)序收斂帶來(lái)影響;芯片線寬的一再縮小,導(dǎo)致互連線的噪聲干擾開(kāi)始影響芯片的整體工作速度和功能的實(shí)現(xiàn);由于存在多個(gè)設(shè)計(jì)變量,而且它們相互依賴,導(dǎo)致時(shí)序收斂變得極其復(fù)雜;電壓降和電遷移問(wèn)題給芯片的工作性能帶來(lái)功耗影響。因此在后端設(shè)計(jì)中工程師需要深入物理設(shè)計(jì),結(jié)合電路特點(diǎn),選取有效的EDA工具,研發(fā)出有針對(duì)性的后端設(shè)計(jì)流程。論文首先簡(jiǎn)單介紹了當(dāng)前集成電路的發(fā)展?fàn)顩r以及國(guó)內(nèi)外研究現(xiàn)況,從設(shè)計(jì)方法出發(fā),引出專用集成電路設(shè)計(jì)的兩種基本方法(展平式設(shè)計(jì)方法和硅虛擬原型設(shè)計(jì)方法),以及本次設(shè)計(jì)所采用Cadence公司的SoC Encounter仿真工具進(jìn)行后端設(shè)計(jì)的流程。在闡述布局布線理論的基礎(chǔ)之上,對(duì)天線效應(yīng)和串?dāng)_問(wèn)題的產(chǎn)生原因及其解決方案進(jìn)行了分析和研究,并成功將芯片布線布通。對(duì)時(shí)鐘樹(shù)綜合理論進(jìn)行了深入分析,建立了合理的時(shí)鐘樹(shù),使芯片的時(shí)序達(dá)到平衡。最后進(jìn)行了靜態(tài)時(shí)序分析、時(shí)序優(yōu)化以及物理驗(yàn)證(DRC和LVS檢查)的工作,完成了后端設(shè)計(jì)的全部流程。在以上各個(gè)設(shè)計(jì)流程設(shè)計(jì)的基礎(chǔ)上,成功研發(fā)出本項(xiàng)目的后端設(shè)計(jì)方案,通過(guò)最終仿真和驗(yàn)證結(jié)果表明,該芯片的性能指標(biāo)如下:工作頻率達(dá)到166.6MZH-166.7MHZ,規(guī)模是800萬(wàn)門,流片面積為5050um×5050um,實(shí)現(xiàn)了存儲(chǔ)速度快、低功耗、面積小等特點(diǎn)。該靜態(tài)隨機(jī)存儲(chǔ)芯片已于2014年11月在北京成功流片。
[Abstract]:With the development of mobile Internet technology, the speed of on-chip system is increasing, which promotes the speed demand of cache. As the core component of cache, static random access memory (RAM) has become the key to improve the speed and reduce the power consumption of the system. Moreover, the updating speed of integrated circuit chips is gradually accelerated, and engineers are eager to shorten the time from initial design to final entry into the market. The traditional full customization design method based on tube level can not meet this demand, and the semi-custom design method based on gate level has become the mainstream in the field of integrated circuit design. The most important innovation in semi-custom design is back-end design, and this work has become the key research topic of various companies and research institutes. The technical level of integrated circuits has entered the deep submicron stage, and engineers are gradually facing more and more problems and more serious challenges in the field of back-end design. For example, the gradual reduction of chip feature size leads to the emergence of interconnection effect; the continuous increase of chip size leads to the rapid expansion of running time, which greatly affects the iterative efficiency of the design process; signal integrity analysis has become a necessary work, which has an impact on the timing convergence of the chip; the line width of the chip is reduced again and again, resulting in the noise interference of the interconnect line begins to affect the overall working speed and function of the chip. Due to the existence of multiple design variables and their interdependence, timing convergence becomes extremely complex, and voltage drop and electromigration problems affect the performance of the chip. Therefore, in the back-end design, engineers need to go deep into the physical design, combined with the circuit characteristics, select effective EDA tools, and develop a targeted back-end design process. Firstly, this paper briefly introduces the development of integrated circuits and the research status at home and abroad. From the design method, two basic methods of special purpose integrated circuit design (flattened design method and silicon virtual prototype design method) are introduced, and the process of back-end design using SoC Encounter simulation tool of Cadence company is introduced. On the basis of expounding the theory of layout and routing, the causes and solutions of antenna effect and crosstalk problem are analyzed and studied, and the chip wiring is successfully distributed. The clock tree synthesis theory is deeply analyzed, and a reasonable clock tree is established to balance the timing of the chip. Finally, the static timing analysis, timing optimization and physical verification (DRC and LVS inspection) are carried out, and the whole process of back-end design is completed. On the basis of the above design flow design, the back-end design scheme of the project is successfully developed. The final simulation and verification results show that the performance index of the chip is as follows: the working frequency is 166.6 MZH 鈮，
本文編號(hào)：2506188
[Abstract]:With the development of mobile Internet technology, the speed of on-chip system is increasing, which promotes the speed demand of cache. As the core component of cache, static random access memory (RAM) has become the key to improve the speed and reduce the power consumption of the system. Moreover, the updating speed of integrated circuit chips is gradually accelerated, and engineers are eager to shorten the time from initial design to final entry into the market. The traditional full customization design method based on tube level can not meet this demand, and the semi-custom design method based on gate level has become the mainstream in the field of integrated circuit design. The most important innovation in semi-custom design is back-end design, and this work has become the key research topic of various companies and research institutes. The technical level of integrated circuits has entered the deep submicron stage, and engineers are gradually facing more and more problems and more serious challenges in the field of back-end design. For example, the gradual reduction of chip feature size leads to the emergence of interconnection effect; the continuous increase of chip size leads to the rapid expansion of running time, which greatly affects the iterative efficiency of the design process; signal integrity analysis has become a necessary work, which has an impact on the timing convergence of the chip; the line width of the chip is reduced again and again, resulting in the noise interference of the interconnect line begins to affect the overall working speed and function of the chip. Due to the existence of multiple design variables and their interdependence, timing convergence becomes extremely complex, and voltage drop and electromigration problems affect the performance of the chip. Therefore, in the back-end design, engineers need to go deep into the physical design, combined with the circuit characteristics, select effective EDA tools, and develop a targeted back-end design process. Firstly, this paper briefly introduces the development of integrated circuits and the research status at home and abroad. From the design method, two basic methods of special purpose integrated circuit design (flattened design method and silicon virtual prototype design method) are introduced, and the process of back-end design using SoC Encounter simulation tool of Cadence company is introduced. On the basis of expounding the theory of layout and routing, the causes and solutions of antenna effect and crosstalk problem are analyzed and studied, and the chip wiring is successfully distributed. The clock tree synthesis theory is deeply analyzed, and a reasonable clock tree is established to balance the timing of the chip. Finally, the static timing analysis, timing optimization and physical verification (DRC and LVS inspection) are carried out, and the whole process of back-end design is completed. On the basis of the above design flow design, the back-end design scheme of the project is successfully developed. The final simulation and verification results show that the performance index of the chip is as follows: the working frequency is 166.6 MZH 鈮，
本文編號(hào)：2506188
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