一種顯化硬件木馬功耗的設(shè)計方法
發(fā)布時間:2019-06-05 20:42
【摘要】:隨著科學(xué)技術(shù)的發(fā)展,集成電路的規(guī)模不斷增大,功能復(fù)雜度不斷提升,半導(dǎo)體設(shè)計制造行業(yè)全球化趨勢不斷加強,迫使芯片設(shè)計和生產(chǎn)的多個環(huán)節(jié)相分離,使得在芯片中植入硬件木馬成為可能。由于硬件木馬一般都是第三方精心設(shè)計實現(xiàn),并且是對底層硬件進(jìn)行的修改,具有隱蔽性強、破壞力大、設(shè)計實現(xiàn)要求高、檢測難度大等特點。為應(yīng)對硬件木馬帶來的安全威脅,本文以基于旁路功耗信息分析的硬件木馬防護(hù)及檢測技術(shù)為基礎(chǔ),研究顯化硬件木馬的方法,主要工作有:隨著集成電路規(guī)模不斷擴(kuò)大,規(guī)模相對很小的木馬電路表現(xiàn)出的旁路信息極易被淹沒。為了顯化硬件木馬功耗,本文提出了一種分時控制的硬件木馬功耗顯化方法。通過對時鐘網(wǎng)絡(luò)的分時模塊控制,降低芯片的瞬時動態(tài)功耗,顯化了硬件木馬功耗。實驗數(shù)據(jù)表明:當(dāng)劃分為3個大小較均衡的模塊時,各周期的峰值功耗可以降到29.9%~36.2%之間;在降低總的瞬時動態(tài)功耗情況下,木馬功耗可以得到平均3.02倍的顯化。功能模塊劃分完成之后,各模塊之間一般有信息交互。為了實際應(yīng)用分時功耗顯化機(jī)制,提出兩種方案:一種是插入隔離鏈方法,該法簡單易用,可自動化實現(xiàn),但面積與延時開銷較大;另一種是棧入式設(shè)計方法,該方法要對設(shè)計中模塊間寄存器棧位關(guān)系進(jìn)行調(diào)整,但是無需插入額外邏輯,面積與延時開銷很小。實驗數(shù)據(jù)表明:對10個模塊的邏輯電路,應(yīng)用分時機(jī)制與棧入式設(shè)計后,在沒有額外增加面積和延時的情況下,各周期的峰值功耗可以降低到5.74%~10.87%之間,大部分集中在10.5%左右;在降低總的瞬時動態(tài)功耗情況下,木馬功耗可以得到平均8.67倍的顯化。
[Abstract]:With the development of science and technology, the scale of integrated circuits is increasing, the complexity of functions is increasing, and the globalization trend of semiconductor design and manufacturing industry is strengthening, which forces the separation of chip design and production. Makes it possible to insert hardware Trojans into the chip. Because the hardware Trojan horse is usually carefully designed and implemented by the third party, and it is a modification of the underlying hardware, it has the characteristics of strong concealment, great destructive power, high design and implementation requirements, difficult detection and so on. In order to deal with the security threat caused by hardware Trojan horse, this paper studies the method of explicit hardware Trojan horse based on the protection and detection technology of hardware Trojan horse based on bypass power information analysis. The main work is as follows: with the continuous expansion of integrated circuit scale, The bypass information shown by the relatively small Trojan horse circuit is easily flooded. In order to display the power consumption of hardware Trojan horse, a time-sharing control method for power consumption visualization of hardware Trojan horse is proposed in this paper. Through the time-sharing module control of the clock network, the instantaneous dynamic power consumption of the chip is reduced, and the power consumption of the hardware Trojan horse is displayed. The experimental data show that when divided into three more balanced modules, the peak power consumption of each cycle can be reduced to 29.9% 鈮,
本文編號:2493810
[Abstract]:With the development of science and technology, the scale of integrated circuits is increasing, the complexity of functions is increasing, and the globalization trend of semiconductor design and manufacturing industry is strengthening, which forces the separation of chip design and production. Makes it possible to insert hardware Trojans into the chip. Because the hardware Trojan horse is usually carefully designed and implemented by the third party, and it is a modification of the underlying hardware, it has the characteristics of strong concealment, great destructive power, high design and implementation requirements, difficult detection and so on. In order to deal with the security threat caused by hardware Trojan horse, this paper studies the method of explicit hardware Trojan horse based on the protection and detection technology of hardware Trojan horse based on bypass power information analysis. The main work is as follows: with the continuous expansion of integrated circuit scale, The bypass information shown by the relatively small Trojan horse circuit is easily flooded. In order to display the power consumption of hardware Trojan horse, a time-sharing control method for power consumption visualization of hardware Trojan horse is proposed in this paper. Through the time-sharing module control of the clock network, the instantaneous dynamic power consumption of the chip is reduced, and the power consumption of the hardware Trojan horse is displayed. The experimental data show that when divided into three more balanced modules, the peak power consumption of each cycle can be reduced to 29.9% 鈮,
本文編號:2493810
本文鏈接:http://sikaile.net/kejilunwen/dianzigongchenglunwen/2493810.html
最近更新
教材專著