OTP邏輯陣列電路設計技術研究
發(fā)布時間：2019-05-30 08:01
【摘要】：隨著微電子技術的快速發(fā)展,可編程邏輯陣列已經經歷幾次變革,從最初的PAL(Programmable Array Logic)到之后的PLA(Programmable Logic Array),再到現(xiàn)在使用最廣泛的CPLD(Complex Programmable Logic Device)和FPGA(Field Programmable Gate Array)。隨著大家對信息安全領域越來越重視,OTP(One Time Programmable)FPGA的研究也慢慢受到各個領域的青睞。但是由于OTP FPGA直接研究的復雜性以及困難性,國內很多研究者們從OTP邏輯陣列電路開始著手,旨在一步步的向前推進,最終研發(fā)出高性能的OTP FPGA。論文的目的是設計一款OTP邏輯陣列電路,旨在驗證自主研究的新型OTP編程位元應用于實際電路的可行性。此次設計的電路主要包括編程位元結構的設計、外圍可編程電路及仿真、回讀測試電路及仿真、邏輯實現(xiàn)功能電路、整體版圖設計以及芯片實物功能測試驗證。通過對新型OTP編程位元擊穿原理的介紹,提出了本次論文使用的新型的OTP編程位元的結構,并對其工作原理進行了詳細說明,在基于該編程位元的結構上,提出了整個邏輯陣列的外圍工作電路的設計方案。其中電壓轉換電路實現(xiàn)了高壓信號被內部電路的安全讀取。2級電荷泵電路將外部高壓信號平穩(wěn)安全的傳遞到編程位元端口,減少了因編程高壓的不穩(wěn)定導致編程位元編程性能的降低甚至失敗。多級譯碼方式配合邏輯陣列的排布降低了整個電路工作延遲時間。讀測試電路利用脈寬展寬電路通過對地址脈沖的展寬,配合靈敏放大器,實現(xiàn)對編程位元數(shù)據(jù)的正確讀取,并配合兩級DICE(Dual Interlocked Storage Cell)鎖存器,將讀取數(shù)據(jù)安全可靠的送出供外部讀取。邏輯實現(xiàn)電路通過CLB(Configurable Logic Block)內部與編程位元的相連,實現(xiàn)了編程數(shù)據(jù)的讀出,并根據(jù)外部需求實現(xiàn)相應的組合或時序功能。整體版圖設計中,本文指出了一些特殊問題的注意事項,并對其提出了相應的解決方案,通過提取相應的寄生參數(shù),利用后仿真工具進行后仿真,根據(jù)仿真結果,修改電路與版圖,最終達到本次的設計目的。通過對流片回來后的芯片進行相應模塊的功能測試,根據(jù)測試結果顯示,本次設計的OTP邏輯陣列電路在編程、回讀以及邏輯功能實現(xiàn)上均能正常的工作,滿足預期的設計期望,達到了本次芯片設計的目的。
[Abstract]:With the rapid development of microelectronics technology, programmable logic array has undergone several changes, from the original PAL (Programmable Array Logic) to the later PLA (Programmable Logic Array), to the most widely used CPLD (Complex Programmable Logic Device) and FPGA (Field Programmable Gate Array). As people pay more and more attention to the field of information security, the research of, OTP (One Time Programmable) FPGA is gradually favored by various fields. However, due to the complexity and difficulty of OTP FPGA direct research, many domestic researchers start with OTP logic array circuits, aiming at advancing step by step, and finally developing high performance OTP FPGA.. The purpose of this paper is to design a OTP logic array circuit to verify the feasibility of applying the new OTP programming bit to the actual circuit. The circuit mainly includes the design of programming bit structure, peripheral programmable circuit and simulation, read back test circuit and simulation, logic realization function circuit, overall layout design and chip physical function test verification. Through the introduction of the breakdown principle of the new OTP programming bit, the structure of the new OTP programming bit used in this paper is put forward, and its working principle is explained in detail. The design scheme of the peripheral working circuit of the whole logic array is put forward. The voltage conversion circuit realizes the safe reading of the high voltage signal by the internal circuit. The 2 stage charge pump circuit transmits the external high voltage signal smoothly and safely to the programming bit port. Because of the instability of programming pressure, the performance of programming bit programming is reduced or even failed. The multistage decoding mode combined with the arrangement of logic array reduces the working delay time of the whole circuit. The reading test circuit uses the pulse width broadening circuit to realize the correct reading of the programming bit metadata and the two-stage DICE (Dual Interlocked Storage Cell) latch by broadening the address pulse and cooperating with the sensitive amplifier. The read data is sent out safely and reliably for external reading. The logic realization circuit is connected with the programming bit through the internal connection of CLB (Configurable Logic Block), which realizes the readout of programming data, and realizes the corresponding combination or timing function according to the external requirements. In the overall layout design, this paper points out some special problems for attention, and puts forward the corresponding solutions. By extracting the corresponding parasitic parameters, using post-simulation tools to carry out post-simulation, according to the simulation results, Modify the circuit and layout, and finally achieve the purpose of this design. Through the function test of the chip after the chip comes back, the test results show that the OTP logic array circuit can work normally in programming, readback and logic function realization, and meets the expected design expectations. The purpose of the chip design has been achieved.
【學位授予單位】：電子科技大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN791
[Abstract]:With the rapid development of microelectronics technology, programmable logic array has undergone several changes, from the original PAL (Programmable Array Logic) to the later PLA (Programmable Logic Array), to the most widely used CPLD (Complex Programmable Logic Device) and FPGA (Field Programmable Gate Array). As people pay more and more attention to the field of information security, the research of, OTP (One Time Programmable) FPGA is gradually favored by various fields. However, due to the complexity and difficulty of OTP FPGA direct research, many domestic researchers start with OTP logic array circuits, aiming at advancing step by step, and finally developing high performance OTP FPGA.. The purpose of this paper is to design a OTP logic array circuit to verify the feasibility of applying the new OTP programming bit to the actual circuit. The circuit mainly includes the design of programming bit structure, peripheral programmable circuit and simulation, read back test circuit and simulation, logic realization function circuit, overall layout design and chip physical function test verification. Through the introduction of the breakdown principle of the new OTP programming bit, the structure of the new OTP programming bit used in this paper is put forward, and its working principle is explained in detail. The design scheme of the peripheral working circuit of the whole logic array is put forward. The voltage conversion circuit realizes the safe reading of the high voltage signal by the internal circuit. The 2 stage charge pump circuit transmits the external high voltage signal smoothly and safely to the programming bit port. Because of the instability of programming pressure, the performance of programming bit programming is reduced or even failed. The multistage decoding mode combined with the arrangement of logic array reduces the working delay time of the whole circuit. The reading test circuit uses the pulse width broadening circuit to realize the correct reading of the programming bit metadata and the two-stage DICE (Dual Interlocked Storage Cell) latch by broadening the address pulse and cooperating with the sensitive amplifier. The read data is sent out safely and reliably for external reading. The logic realization circuit is connected with the programming bit through the internal connection of CLB (Configurable Logic Block), which realizes the readout of programming data, and realizes the corresponding combination or timing function according to the external requirements. In the overall layout design, this paper points out some special problems for attention, and puts forward the corresponding solutions. By extracting the corresponding parasitic parameters, using post-simulation tools to carry out post-simulation, according to the simulation results, Modify the circuit and layout, and finally achieve the purpose of this design. Through the function test of the chip after the chip comes back, the test results show that the OTP logic array circuit can work normally in programming, readback and logic function realization, and meets the expected design expectations. The purpose of the chip design has been achieved.
【學位授予單位】：電子科技大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN791
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