基于改進(jìn)CORDIC算法的直接數(shù)字頻率合成器研究
發(fā)布時(shí)間：2019-05-18 03:22
【摘要】：直接數(shù)字頻率合成器簡(jiǎn)稱為DDS,這是一種最近一些年才發(fā)展起來的新型的頻率合成技術(shù)。這種技術(shù)依托于快速發(fā)展的集成電路技術(shù),現(xiàn)代集成電路技術(shù)根據(jù)摩爾定律的預(yù)測(cè)在不斷的進(jìn)步,直接數(shù)字頻率合成器在這個(gè)環(huán)境之下也受到越來越多的重視。這種頻率合成技術(shù)比以前的傳統(tǒng)頻率合成技術(shù)分辨率更高,轉(zhuǎn)換時(shí)間更快,噪聲更低,所以在許多的電子系統(tǒng)當(dāng)中被廣泛的應(yīng)用。相位累加器、相幅轉(zhuǎn)換器、數(shù)模轉(zhuǎn)換器和低通濾波器這幾個(gè)部分構(gòu)成了直接數(shù)字頻率合成器。以前的直接數(shù)字頻率合成器一般都是采用查找表ROM或者CORDIC算法來實(shí)現(xiàn)相幅轉(zhuǎn)換器,這兩種方法各有優(yōu)點(diǎn),現(xiàn)在一般采用的是CORDIC算法實(shí)現(xiàn),這種方法電路比較簡(jiǎn)單,占用的存儲(chǔ)容量也很小。本文提出的直接數(shù)字頻率合成器使用的是查找表ROM和CORDIC算法結(jié)合使用,能夠減小噪聲、減小轉(zhuǎn)換時(shí)間、提高SFDR。同時(shí)這種方法能夠減少計(jì)算迭代的次數(shù),從而減少硬件電路的資源消耗。本文采用相位累加器的位寬是32位,相位累加器輸出截?cái)嘀笫?9位,高3位用來進(jìn)行區(qū)塊選擇,接下來的7位用來進(jìn)行查找表ROM尋址,低9位用于CORDIC算法的旋轉(zhuǎn)計(jì)算。RTL級(jí)的代碼實(shí)現(xiàn)進(jìn)行仿真時(shí),SFDR均能夠達(dá)到113dB左右,有比較高的無雜散動(dòng)態(tài)范圍。本文的DDS有三種工作模式:斜坡模式,Profile模式和單頻模式。本篇文章對(duì)直接數(shù)字合成器的許多方面進(jìn)行了詳細(xì)的介紹,包括其概念、國(guó)內(nèi)外的發(fā)展?fàn)顩r、其基本的結(jié)構(gòu)原理。然后是本文的主要工作點(diǎn),也就是相位幅度轉(zhuǎn)換器的改進(jìn)。最后對(duì)本文提出的DDS進(jìn)行了邏輯綜合和后端物理設(shè)計(jì)。進(jìn)行邏輯綜合的時(shí)候采用的工藝庫(kù)是中芯國(guó)際的SMIC 0.18μm 1.8V 1P6M CMOS庫(kù),邏輯綜合之后的芯片單元的總數(shù)是36700個(gè),31074個(gè)組合邏輯單元,5623個(gè)時(shí)序邏輯單元,6306063.20μm2的總面積。1235.3mW的動(dòng)態(tài)功耗和465.65μW的靜態(tài)功耗,總的功耗是1235.8mW。
[Abstract]:Direct digital frequency synthesizer (DDS,) is a new frequency synthesis technology which has only been developed in recent years. This technology relies on the rapid development of integrated circuit technology. According to Moore's law, modern integrated circuit technology is making continuous progress, and direct digital frequency synthesizer has been paid more and more attention in this environment. Compared with the previous traditional frequency synthesis technology, this frequency synthesis technology has higher resolution, faster conversion time and lower noise, so it is widely used in many electronic systems. Phase accumulator, phase amplitude converter, digital-to-analog converter and low-pass filter constitute direct digital frequency synthesizer. In the past, the direct digital frequency synthesizer generally used the look-up table ROM or CORDIC algorithm to realize the phase amplitude converter. These two methods have their own advantages. Now the direct digital frequency synthesizer is usually implemented by CORDIC algorithm. This method circuit is relatively simple. The storage capacity occupied is also very small. The direct digital frequency synthesizer proposed in this paper uses the combination of look-up table ROM and CORDIC algorithm, which can reduce noise, reduce conversion time and improve SFDR.. At the same time, this method can reduce the number of iterations, thus reducing the resource consumption of hardware circuits. In this paper, the bit width of the phase accumulator is 32 bits, the output of the phase accumulator is 19 bits, the high 3 bits are used for block selection, and the next 7 bits are used for ROM addressing of the lookup table. The low 9 bits are used in the rotation calculation of CORDIC algorithm. When the code implementation at RTL level is simulated, the SFDR can reach about 113dB, and has a high non-stray dynamic range. There are three working modes of DDS in this paper: slope mode, Profile mode and single frequency mode. In this paper, many aspects of direct digital synthesizer are introduced in detail, including its concept, development at home and abroad, and its basic structure and principle. Then there is the main working point of this paper, that is, the improvement of phase amplitude converter. Finally, the logic synthesis and back-end physical design of DDS proposed in this paper are carried out. The process library used in logic synthesis is SMIC 0.18 渭 m 1.8V 1P6M CMOS library. The total number of chip units after logic synthesis is 36700, 31074 combinational logic units and 5623 sequential logic units. The total area of 6306063.20 渭 m ~ 2. 1235.3 mW dynamic power consumption and 465.65 渭 W static power consumption, the total power consumption is 1235.8 MW.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN741
本文編號(hào)：2479630
[Abstract]:Direct digital frequency synthesizer (DDS,) is a new frequency synthesis technology which has only been developed in recent years. This technology relies on the rapid development of integrated circuit technology. According to Moore's law, modern integrated circuit technology is making continuous progress, and direct digital frequency synthesizer has been paid more and more attention in this environment. Compared with the previous traditional frequency synthesis technology, this frequency synthesis technology has higher resolution, faster conversion time and lower noise, so it is widely used in many electronic systems. Phase accumulator, phase amplitude converter, digital-to-analog converter and low-pass filter constitute direct digital frequency synthesizer. In the past, the direct digital frequency synthesizer generally used the look-up table ROM or CORDIC algorithm to realize the phase amplitude converter. These two methods have their own advantages. Now the direct digital frequency synthesizer is usually implemented by CORDIC algorithm. This method circuit is relatively simple. The storage capacity occupied is also very small. The direct digital frequency synthesizer proposed in this paper uses the combination of look-up table ROM and CORDIC algorithm, which can reduce noise, reduce conversion time and improve SFDR.. At the same time, this method can reduce the number of iterations, thus reducing the resource consumption of hardware circuits. In this paper, the bit width of the phase accumulator is 32 bits, the output of the phase accumulator is 19 bits, the high 3 bits are used for block selection, and the next 7 bits are used for ROM addressing of the lookup table. The low 9 bits are used in the rotation calculation of CORDIC algorithm. When the code implementation at RTL level is simulated, the SFDR can reach about 113dB, and has a high non-stray dynamic range. There are three working modes of DDS in this paper: slope mode, Profile mode and single frequency mode. In this paper, many aspects of direct digital synthesizer are introduced in detail, including its concept, development at home and abroad, and its basic structure and principle. Then there is the main working point of this paper, that is, the improvement of phase amplitude converter. Finally, the logic synthesis and back-end physical design of DDS proposed in this paper are carried out. The process library used in logic synthesis is SMIC 0.18 渭 m 1.8V 1P6M CMOS library. The total number of chip units after logic synthesis is 36700, 31074 combinational logic units and 5623 sequential logic units. The total area of 6306063.20 渭 m ~ 2. 1235.3 mW dynamic power consumption and 465.65 渭 W static power consumption, the total power consumption is 1235.8 MW.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN741
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