納米工藝ASIC物理設(shè)計(jì)的實(shí)現(xiàn)和信號完整性優(yōu)化
發(fā)布時間：2019-04-25 17:03
【摘要】：信號完整性是電子信號攜帶信息的可靠性,和抵抗來自附近信號高頻電磁干擾影響的能力。當(dāng)電子信號攜帶的信息失真,或高頻電磁干擾對電子信號造成了影響時,即出現(xiàn)了所謂的信號完整性問題。目前,集成電路工藝已發(fā)展到納米水平,時鐘頻率達(dá)到上GHz。伴隨著半導(dǎo)體工藝的不斷發(fā)展,集成電路的線間互連問題已經(jīng)成為決定整個芯片性能、功耗、可靠性及成本的主導(dǎo)因素。信號完整性問題正成為制約超大規(guī)模集成電路繼續(xù)發(fā)展的主要瓶頸。ASIC物理設(shè)計(jì)中的信號完整性問題可分為兩類:串?dāng)_噪聲和電遷移。串?dāng)_噪聲由連線間的耦合電容引起,其不僅影響電路延遲,引起時序違例(串?dāng)_delta延遲),還會影響電路功能(串?dāng)_毛刺),導(dǎo)致芯片故障。電遷移由芯片內(nèi)部的寄生電阻引起,也會引起芯片性能的降低,甚至導(dǎo)致芯片失效。本文的研究基于ASIC物理設(shè)計(jì),對納米工藝下信號完整性問題進(jìn)行分析并提出預(yù)防策略和修復(fù)方法。首先,對連線延遲和寄生參數(shù)提取進(jìn)行建模和理論分析,探索減少串?dāng)_噪聲的方法,并通過與業(yè)界常用的物理設(shè)計(jì)工具IC Compiler相結(jié)合來闡述以預(yù)防為主,進(jìn)而修復(fù)達(dá)到串?dāng)_噪聲收斂的優(yōu)化方法。最后,將此方法應(yīng)用于實(shí)驗(yàn)室具體的項(xiàng)目中,驗(yàn)證結(jié)果表明預(yù)防策略能大幅減少信號完整性問題,修復(fù)方法能有效減少迭代次數(shù),達(dá)到快速解決信號完整性問題的效果。針對金屬電遷移問題,文中首先介紹物理設(shè)計(jì)工具IC Compiler分析電遷移的方法,從方法中用到的各個參數(shù)尋找突破口,優(yōu)化電遷移。并且也通過實(shí)驗(yàn)室具體項(xiàng)目驗(yàn)證了此方法對電遷移有很好的優(yōu)化效果。本文的實(shí)際意義是在物理設(shè)計(jì)方面提出了納米工藝下信號完整性問題的優(yōu)化方法,完善了實(shí)驗(yàn)室納米工藝物理設(shè)計(jì)流程,并且通過實(shí)驗(yàn)室實(shí)際SHA-256模塊物理設(shè)計(jì)項(xiàng)目,很好地驗(yàn)證了此方法的可行性。
[Abstract]:Signal integrity is the reliability of electronic signals to carry information and the ability to resist high-frequency electromagnetic interference from nearby signals. The so-called signal integrity problem arises when the information distortion carried by the electronic signal, or the high frequency electromagnetic interference (HEMI), affects the electronic signal. At present, the integrated circuit technology has developed to the nanometer level, and the clock frequency is up to GHz. With the development of semiconductor technology, the inter-line interconnection of integrated circuits has become the leading factor to determine the performance, power consumption, reliability and cost of the whole chip. Signal integrity is becoming the main bottleneck restricting the development of VLSI. Signal integrity problems in ASIC physical design can be divided into two categories: crosstalk noise and electromigration. Crosstalk noise is caused by coupling capacitance between wires, which not only affects circuit delay, causes timing violation (crosstalk delta delay), but also affects circuit function (crosstalk burr), leading to chip failure. Electromigration is caused by the parasitic resistance in the chip, which also leads to the degradation of the chip performance and even the failure of the chip. In this paper, based on the physical design of ASIC, the problem of signal integrity in nano-technology is analyzed and the preventive strategy and repair method are put forward. Firstly, modeling and theoretical analysis are carried out on the extraction of line delay and parasitic parameters, and the methods of reducing crosstalk noise are explored, and the prevention is mainly explained by combining with the physical design tool IC Compiler, which is commonly used in the industry. Furthermore, the optimization method which achieves crosstalk noise convergence is repaired. Finally, this method is applied to specific laboratory projects. The verification results show that the preventive strategy can greatly reduce the signal integrity problem, and the repair method can effectively reduce the number of iterations to quickly solve the signal integrity problem. In order to solve the problem of metal electromigration, the method of analyzing electromigration by physical design tool IC Compiler is introduced in this paper, and the breakthrough point is found from the parameters used in the method to optimize the electromigration. It is also verified that this method has a good optimization effect on electromigration through specific laboratory projects. The practical significance of this paper is to put forward the optimization method of signal integrity under nano-technology in physical design, perfect the physical design flow of nano-process in laboratory, and through the physical design project of SHA-256 module in laboratory, The feasibility of this method is well verified.
【學(xué)位授予單位】：北京工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN402
本文編號：2465306
[Abstract]:Signal integrity is the reliability of electronic signals to carry information and the ability to resist high-frequency electromagnetic interference from nearby signals. The so-called signal integrity problem arises when the information distortion carried by the electronic signal, or the high frequency electromagnetic interference (HEMI), affects the electronic signal. At present, the integrated circuit technology has developed to the nanometer level, and the clock frequency is up to GHz. With the development of semiconductor technology, the inter-line interconnection of integrated circuits has become the leading factor to determine the performance, power consumption, reliability and cost of the whole chip. Signal integrity is becoming the main bottleneck restricting the development of VLSI. Signal integrity problems in ASIC physical design can be divided into two categories: crosstalk noise and electromigration. Crosstalk noise is caused by coupling capacitance between wires, which not only affects circuit delay, causes timing violation (crosstalk delta delay), but also affects circuit function (crosstalk burr), leading to chip failure. Electromigration is caused by the parasitic resistance in the chip, which also leads to the degradation of the chip performance and even the failure of the chip. In this paper, based on the physical design of ASIC, the problem of signal integrity in nano-technology is analyzed and the preventive strategy and repair method are put forward. Firstly, modeling and theoretical analysis are carried out on the extraction of line delay and parasitic parameters, and the methods of reducing crosstalk noise are explored, and the prevention is mainly explained by combining with the physical design tool IC Compiler, which is commonly used in the industry. Furthermore, the optimization method which achieves crosstalk noise convergence is repaired. Finally, this method is applied to specific laboratory projects. The verification results show that the preventive strategy can greatly reduce the signal integrity problem, and the repair method can effectively reduce the number of iterations to quickly solve the signal integrity problem. In order to solve the problem of metal electromigration, the method of analyzing electromigration by physical design tool IC Compiler is introduced in this paper, and the breakthrough point is found from the parameters used in the method to optimize the electromigration. It is also verified that this method has a good optimization effect on electromigration through specific laboratory projects. The practical significance of this paper is to put forward the optimization method of signal integrity under nano-technology in physical design, perfect the physical design flow of nano-process in laboratory, and through the physical design project of SHA-256 module in laboratory, The feasibility of this method is well verified.
【學(xué)位授予單位】：北京工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN402
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