基于BCD工藝的ESD器件性能研究與優(yōu)化
發(fā)布時(shí)間：2019-04-23 23:25
【摘要】：隨著集成電路的發(fā)展,高壓功率集成電路在汽車電子、顯示驅(qū)動(dòng)等方面顯示出巨大應(yīng)用前景。而靜電放電(Electrostatic Discharge,ESD)對高壓集成電路存在巨大的潛在威脅。在BCD (Bipolar-CMOS-DMOS)工藝下,由于器件面臨著更高的工作電壓、更加惡劣的工作環(huán)境等問題,使得高壓集成電路的靜電防護(hù)設(shè)計(jì)面臨著更加嚴(yán)峻的挑戰(zhàn)。同時(shí),由于工藝對ESD防護(hù)設(shè)計(jì)有著巨大的影響,所以必須單獨(dú)為不同的工藝設(shè)計(jì)ESD防護(hù)器件,這也增大了ESD防護(hù)設(shè)計(jì)的難度和工作量。本文基于0.18μm BCD工藝,研究了相關(guān)高壓器件的ESD特性。本文首先對ESD的基本理論進(jìn)行了介紹,包括ESD防護(hù)基本理論、ESD測試模型以及ESD設(shè)計(jì)窗口。在此基礎(chǔ)上,引入二極管、BJT、LDMOS(Lateral Diffused MOS)以及SCR(Silicon Controlled Rectifier)等常規(guī)的ESD防護(hù)器件,并分別介紹了這些器件在ESD事件下的工作原理。并通過對常規(guī)LDMOS及SCR防護(hù)器件的分析,闡述這兩類ESD防護(hù)器件存在的問題。由于LDMOS器件存在電流不均勻?qū)?導(dǎo)致LDMOS器件的ESD防護(hù)能力低下。為了優(yōu)化和改進(jìn)LDMOS器件的特性,本文在BCD工藝下設(shè)計(jì)了相關(guān)的LDMOS器件并進(jìn)行了測試。TLP測試結(jié)果表明,改變LDMOS器件的溝道長度對其ESD性能基本沒有影響。同時(shí),硅化物工藝下拉大漏到柵的距離也很難形成有效的鎮(zhèn)流效應(yīng)。通過嵌入SCR到LDMOS器件中是一種提高LDMOS器件ESD防護(hù)能力的有效手段。其中分割型SCR-LDMOS器件的ESD失效電流和P+/N+的比率成正相關(guān)。由于SCR存在大回滯現(xiàn)象,所以必須提高SCR類型器件的維持電壓以及降低其觸發(fā)電壓。對于單向SCR大回滯類型器件,研究了MLSCR結(jié)構(gòu)和雙觸發(fā)類型SCR結(jié)構(gòu)來降低觸發(fā)電壓,TLP測試結(jié)果表明該兩種方案均能降低SCR的觸發(fā)電壓。然后引入了提高維持電壓的結(jié)構(gòu)如分割型SCR結(jié)構(gòu)、高維持電壓的HHV-SCR結(jié)構(gòu)。最后提出了RC輔助觸發(fā)的SCR結(jié)構(gòu),該結(jié)構(gòu)可以提供非回滯特性的ESD曲線,該結(jié)構(gòu)能夠?qū)㈦妷恒Q位在10V以下并提供高達(dá)9KV的HBM防護(hù)能力。適用于電源軌之間的電壓鉗位器件。為了減小版圖面積,本文最后給出了雙向SCR結(jié)構(gòu)設(shè)計(jì)以及其中的一個(gè)改進(jìn)型雙向SCR結(jié)構(gòu)。
[Abstract]:With the development of integrated circuits, high-voltage power integrated circuits show great application prospects in automotive electronics, display drive and so on. Electrostatic discharge (Electrostatic Discharge,ESD) is a potential threat to high voltage integrated circuits (HV IC). In the BCD (Bipolar-CMOS-DMOS) process, the electrostatic protection design of high voltage integrated circuits faces more severe challenges due to the higher working voltage and worse working environment. At the same time, because of the great influence of the process on the ESD protection design, it is necessary to design the ESD protection devices for different processes, which increases the difficulty and workload of the ESD protection design. In this paper, the ESD characteristics of correlation high voltage devices are studied based on 0.18 渭 m BCD process. This paper first introduces the basic theory of ESD, including the basic theory of ESD protection, ESD test model and ESD design window. On this basis, the conventional ESD protective devices such as diodes, BJT,LDMOS (Lateral Diffused MOS) and SCR (Silicon Controlled Rectifier) are introduced, and the working principles of these devices under ESD events are introduced respectively. Based on the analysis of conventional LDMOS and SCR protective devices, the existing problems of these two types of ESD protective devices are expounded. Due to the non-uniform current conduction of LDMOS devices, the ESD protection ability of LDMOS devices is low. In order to optimize and improve the characteristics of LDMOS devices, the related LDMOS devices are designed and tested in BCD process. The results show that changing the channel length of LDMOS devices has little effect on the performance of ESD devices. At the same time, it is very difficult to form effective ballasting effect by widening the distance from drain to gate in silicide process. Embedding SCR into LDMOS devices is an effective way to improve the ESD protection ability of LDMOS devices. The ESD failure current of split SCR-LDMOS devices is positively correlated with the P / N ratio. Because of the large hysteresis in SCR, it is necessary to increase the maintenance voltage and reduce the trigger voltage of SCR devices. For unidirectional SCR devices with large hysteresis, the MLSCR structure and the double trigger type SCR structure are studied to reduce the trigger voltage. The TLP test results show that both schemes can reduce the trigger voltage of SCR. Then, the structure of improving maintenance voltage, such as split SCR structure and high maintenance voltage HHV-SCR structure, is introduced. Finally, a RC-aided triggered SCR structure is proposed, which can provide ESD curves with non-hysteresis characteristics. The structure can clamp voltage below 10V and provide HBM protection as high as 9KV. Suitable for voltage clamp devices between power rails. In order to reduce the layout area, the design of bi-directional SCR structure and an improved bi-directional SCR structure are presented in this paper.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN386
本文編號：2463899
[Abstract]:With the development of integrated circuits, high-voltage power integrated circuits show great application prospects in automotive electronics, display drive and so on. Electrostatic discharge (Electrostatic Discharge,ESD) is a potential threat to high voltage integrated circuits (HV IC). In the BCD (Bipolar-CMOS-DMOS) process, the electrostatic protection design of high voltage integrated circuits faces more severe challenges due to the higher working voltage and worse working environment. At the same time, because of the great influence of the process on the ESD protection design, it is necessary to design the ESD protection devices for different processes, which increases the difficulty and workload of the ESD protection design. In this paper, the ESD characteristics of correlation high voltage devices are studied based on 0.18 渭 m BCD process. This paper first introduces the basic theory of ESD, including the basic theory of ESD protection, ESD test model and ESD design window. On this basis, the conventional ESD protective devices such as diodes, BJT,LDMOS (Lateral Diffused MOS) and SCR (Silicon Controlled Rectifier) are introduced, and the working principles of these devices under ESD events are introduced respectively. Based on the analysis of conventional LDMOS and SCR protective devices, the existing problems of these two types of ESD protective devices are expounded. Due to the non-uniform current conduction of LDMOS devices, the ESD protection ability of LDMOS devices is low. In order to optimize and improve the characteristics of LDMOS devices, the related LDMOS devices are designed and tested in BCD process. The results show that changing the channel length of LDMOS devices has little effect on the performance of ESD devices. At the same time, it is very difficult to form effective ballasting effect by widening the distance from drain to gate in silicide process. Embedding SCR into LDMOS devices is an effective way to improve the ESD protection ability of LDMOS devices. The ESD failure current of split SCR-LDMOS devices is positively correlated with the P / N ratio. Because of the large hysteresis in SCR, it is necessary to increase the maintenance voltage and reduce the trigger voltage of SCR devices. For unidirectional SCR devices with large hysteresis, the MLSCR structure and the double trigger type SCR structure are studied to reduce the trigger voltage. The TLP test results show that both schemes can reduce the trigger voltage of SCR. Then, the structure of improving maintenance voltage, such as split SCR structure and high maintenance voltage HHV-SCR structure, is introduced. Finally, a RC-aided triggered SCR structure is proposed, which can provide ESD curves with non-hysteresis characteristics. The structure can clamp voltage below 10V and provide HBM protection as high as 9KV. Suitable for voltage clamp devices between power rails. In order to reduce the layout area, the design of bi-directional SCR structure and an improved bi-directional SCR structure are presented in this paper.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN386
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