基于HDL代碼的數(shù)字電路性能評(píng)估與PAITS優(yōu)化
發(fā)布時(shí)間：2019-04-04 12:40
【摘要】：提高源代碼的質(zhì)量是加快SoC/ASIC芯片設(shè)計(jì)進(jìn)度、提高其質(zhì)量的重要手段。而RTL綜合器進(jìn)行的綜合工作與HDL源代碼間的設(shè)計(jì)迭代,也是影響芯片設(shè)計(jì)進(jìn)度重要環(huán)節(jié)。高質(zhì)量的RTL代碼可以得到更優(yōu)的綜合結(jié)果,減少在電路綜合與HDL代碼編寫之間的設(shè)計(jì)迭代,從而縮短電路設(shè)計(jì)時(shí)間并提高設(shè)計(jì)效率。為了提高源代碼的研發(fā)質(zhì)量、盡早發(fā)現(xiàn)芯片設(shè)計(jì)階段存在的缺陷,縮短電路設(shè)計(jì)迭代過程、提高電路設(shè)計(jì)效率,從而加速SoC/ASIC的設(shè)計(jì)過程,本文認(rèn)為可以從以下兩個(gè)方面入手:其一,開發(fā)出具有更好時(shí)序的HDL代碼,為綜合和最終布線完成后遺留較少的時(shí)序偏差問題,減少在門級(jí)需要解決的時(shí)序問題;其二,需要一種好的方法來優(yōu)化門級(jí)電路,使得在可以的情況下盡可能不追溯到HDL代碼以減少設(shè)計(jì)工作的迭代。本文分別為以上兩種方案的設(shè)計(jì)與實(shí)現(xiàn)進(jìn)行了研究,提出了基于HDL代碼的數(shù)字電路靜態(tài)時(shí)序分析和數(shù)字電路并行拓?fù)渑判騼?yōu)化(PAITS)算法。本文的主要成果有:1.針對(duì)開發(fā)出具有更好時(shí)序的代碼這一問題,提出了基于HDL代碼的數(shù)字電路靜態(tài)時(shí)序分析。HDL代碼的數(shù)字電路靜態(tài)時(shí)序分析進(jìn)行在集成電路設(shè)計(jì)的編譯仿真之后、邏輯綜合之前,是通過根據(jù)代碼預(yù)判電路結(jié)構(gòu)、對(duì)門延時(shí)建模,從而達(dá)到分析電路時(shí)序情況的目的。本文使用樹型結(jié)構(gòu)分別對(duì)HDL代碼中的純組合邏輯語(yǔ)句和會(huì)綜合出寄存器的語(yǔ)句進(jìn)行時(shí)序路徑建模,將電路中的每條時(shí)序路徑建立為有輸入和輸出的頂點(diǎn),指向頂點(diǎn)的邊表示輸入信號(hào),從頂點(diǎn)出發(fā)的邊為被賦值變量或電路輸出,頂點(diǎn)的權(quán)值為路徑的延時(shí)。然后通過對(duì)HDL代碼中的語(yǔ)句進(jìn)行延時(shí)建模,即可對(duì)電路中的各個(gè)路徑給出了延時(shí)的預(yù)估。由此可以分析得到電路的關(guān)鍵路徑及其延時(shí),從而分析電路是否滿足目標(biāo)時(shí)序要求。實(shí)驗(yàn)結(jié)果顯示,靜態(tài)時(shí)序分析得到的電路關(guān)鍵路徑,皆包含在本算法分析后找到的電路關(guān)鍵路徑中,本方法預(yù)估的電路延時(shí)與STA分析結(jié)果的相對(duì)誤差在30%內(nèi)。2.針對(duì)當(dāng)數(shù)字電路的時(shí)序難以滿足優(yōu)化目標(biāo)時(shí)要進(jìn)行設(shè)計(jì)迭代的問題,依據(jù)電路并行工作的特性,改進(jìn)產(chǎn)生線性序列的拓?fù)渑判蛩惴?提出了并行全入度拓?fù)渑判?PAITS),而后根據(jù)PAITS提出數(shù)字電路PAITS優(yōu)化算法。該優(yōu)化算法首先使用分析有向圖的思想分析電路結(jié)構(gòu),對(duì)電路的有向圖進(jìn)行PAITS,得到電路中插入寄存器可選位置的詳細(xì)信息,再根據(jù)排序得到的信息和優(yōu)化目標(biāo),直接選擇最佳位置,通過重寫網(wǎng)表插入流水線、優(yōu)化電路,無需設(shè)計(jì)迭代。且與有效重定時(shí)判定經(jīng)典算法FEAS的時(shí)間復(fù)雜度O(|V|?|E|)相比,PAITS擁有較低的時(shí)間復(fù)雜度O(f?|V|+|E|),其中f為電路扇出約束。實(shí)驗(yàn)結(jié)果表明,插入同樣級(jí)數(shù)的寄存器時(shí),使用本算法優(yōu)化的電路與重定時(shí)優(yōu)化的電路相比電路面積較之少了20-40%。
[Abstract]:Improving the quality of source code is an important means to speed up the design progress and improve the quality of SoC/ASIC chip. The iteration between the synthesis work of RTL synthesizer and the source code of HDL is also an important link that affects the progress of chip design. The high-quality RTL code can get better synthesis results, reduce the design iteration between circuit synthesis and HDL code writing, thus shorten the circuit design time and improve the design efficiency. In order to improve the research and development quality of the source code, the defects in the chip design stage are discovered as soon as possible, the iterative process of circuit design is shortened, and the circuit design efficiency is improved, so as to accelerate the design process of SoC/ASIC. In this paper, we think we can start with the following two aspects: firstly, we can develop HDL code with better timing, which can reduce the timing problems that need to be solved at the gate level for the sake of fewer timing deviation problems left after synthesis and final wiring; Secondly, a good method is needed to optimize gate-level circuits so as not to trace back to the HDL code as far as possible so as to reduce the iteration of design work. In this paper, the design and implementation of the above two schemes are studied, and the static timing analysis of digital circuits based on HDL code and the parallel topology sorting optimization (PAITS) algorithm of digital circuits are proposed. The main results of this paper are as follows: 1. In order to solve the problem of developing code with better timing, the static timing analysis of digital circuit based on HDL code is proposed. After compiling and simulation of integrated circuit design, before logic synthesis, the static timing analysis of digital circuit based on HDL code is carried out. By pre-judging the structure of the circuit according to the code and modeling the gate delay, the purpose of analyzing the timing of the circuit is achieved. In this paper, the tree structure is used to model the sequential path of the pure combinatorial logic statements in HDL code and the statements that synthesize registers, and each sequential path in the circuit is established as a vertex with input and output. The edge pointing to the vertex represents the input signal, the edge starting from the vertex is assigned variable or circuit output, and the weight of vertex is the delay of path. Then the delay model of the statements in the HDL code can be used to estimate the delay of each path in the circuit. Therefore, the critical path and delay of the circuit can be analyzed, and then it can be analyzed whether the circuit can meet the requirement of the target timing. The experimental results show that the circuit critical paths obtained by static time series analysis are included in the circuit critical paths found after the analysis of this algorithm. The relative error between the circuit delay predicted by this method and the results of STA analysis is within 30%. In order to solve the problem of design iteration when the timing of digital circuit is difficult to meet the optimization objective, according to the characteristics of circuit parallel work, the topological sorting algorithm of generating linear sequence is improved, and the parallel total degree topological ranking (PAITS),) is proposed. Then, based on PAITS, a digital circuit PAITS optimization algorithm is proposed. The algorithm first analyzes the circuit structure using the idea of analyzing directed graph, carries on the PAITS, to the directed graph of the circuit to get the detailed information of the optional position of the insert register in the circuit, and then obtains the information according to the sort and the optimization goal. Directly select the best location by rewriting the mesh to insert pipelining, optimize the circuit without the need to design iterations. Compared with the time complexity O (| V |? | E |) of the classical algorithm FEAS, PAITS has a lower time complexity O (f? | V | E |), where f is a circuit fan-out constraint. The experimental results show that when the registers of the same series are inserted, the area of the circuit optimized by this algorithm is 20% less than that of the retiming optimized circuit.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN79
本文編號(hào)：2453820
[Abstract]:Improving the quality of source code is an important means to speed up the design progress and improve the quality of SoC/ASIC chip. The iteration between the synthesis work of RTL synthesizer and the source code of HDL is also an important link that affects the progress of chip design. The high-quality RTL code can get better synthesis results, reduce the design iteration between circuit synthesis and HDL code writing, thus shorten the circuit design time and improve the design efficiency. In order to improve the research and development quality of the source code, the defects in the chip design stage are discovered as soon as possible, the iterative process of circuit design is shortened, and the circuit design efficiency is improved, so as to accelerate the design process of SoC/ASIC. In this paper, we think we can start with the following two aspects: firstly, we can develop HDL code with better timing, which can reduce the timing problems that need to be solved at the gate level for the sake of fewer timing deviation problems left after synthesis and final wiring; Secondly, a good method is needed to optimize gate-level circuits so as not to trace back to the HDL code as far as possible so as to reduce the iteration of design work. In this paper, the design and implementation of the above two schemes are studied, and the static timing analysis of digital circuits based on HDL code and the parallel topology sorting optimization (PAITS) algorithm of digital circuits are proposed. The main results of this paper are as follows: 1. In order to solve the problem of developing code with better timing, the static timing analysis of digital circuit based on HDL code is proposed. After compiling and simulation of integrated circuit design, before logic synthesis, the static timing analysis of digital circuit based on HDL code is carried out. By pre-judging the structure of the circuit according to the code and modeling the gate delay, the purpose of analyzing the timing of the circuit is achieved. In this paper, the tree structure is used to model the sequential path of the pure combinatorial logic statements in HDL code and the statements that synthesize registers, and each sequential path in the circuit is established as a vertex with input and output. The edge pointing to the vertex represents the input signal, the edge starting from the vertex is assigned variable or circuit output, and the weight of vertex is the delay of path. Then the delay model of the statements in the HDL code can be used to estimate the delay of each path in the circuit. Therefore, the critical path and delay of the circuit can be analyzed, and then it can be analyzed whether the circuit can meet the requirement of the target timing. The experimental results show that the circuit critical paths obtained by static time series analysis are included in the circuit critical paths found after the analysis of this algorithm. The relative error between the circuit delay predicted by this method and the results of STA analysis is within 30%. In order to solve the problem of design iteration when the timing of digital circuit is difficult to meet the optimization objective, according to the characteristics of circuit parallel work, the topological sorting algorithm of generating linear sequence is improved, and the parallel total degree topological ranking (PAITS),) is proposed. Then, based on PAITS, a digital circuit PAITS optimization algorithm is proposed. The algorithm first analyzes the circuit structure using the idea of analyzing directed graph, carries on the PAITS, to the directed graph of the circuit to get the detailed information of the optional position of the insert register in the circuit, and then obtains the information according to the sort and the optimization goal. Directly select the best location by rewriting the mesh to insert pipelining, optimize the circuit without the need to design iterations. Compared with the time complexity O (| V |? | E |) of the classical algorithm FEAS, PAITS has a lower time complexity O (f? | V | E |), where f is a circuit fan-out constraint. The experimental results show that when the registers of the same series are inserted, the area of the circuit optimized by this algorithm is 20% less than that of the retiming optimized circuit.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN79
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