高精度sigma-delta DAC中數(shù)字ASIC的設(shè)計
發(fā)布時間：2019-03-25 21:36
【摘要】：微機械陀螺數(shù)字化是目前慣性傳感器系統(tǒng)領(lǐng)域的研究熱點之一,數(shù)字化的微機械陀螺系統(tǒng)已逐漸成為設(shè)計主流。在數(shù)字化微機械陀螺系統(tǒng)中,高精度的DAC是其關(guān)鍵模塊之一。本論文旨在研究一種專門應(yīng)用于微機械陀螺系統(tǒng)中的高精度sigma-delta DAC數(shù)字前端集成電路(ASIC)設(shè)計。本文工作內(nèi)容包含三個主要模塊:數(shù)字插值濾波器、sigma-delta調(diào)制器、DEM動態(tài)單元匹配模塊。其中數(shù)字插值濾波器采用多級數(shù)字濾波器級聯(lián)結(jié)構(gòu)設(shè)計,級聯(lián)結(jié)構(gòu)中包括兩級半帶濾波器、CIC補償濾波器與CIC濾波器,在對傳統(tǒng)半帶濾波器分析的基礎(chǔ)上,提出了一種魯棒性半帶濾波器結(jié)構(gòu),這種結(jié)構(gòu)對傳統(tǒng)半帶濾波器傳遞函數(shù)進行了改進,使其幅頻特性對濾波器系數(shù)敏感程度較低,而且該結(jié)構(gòu)具有硬件電路消耗低、電路工作速度快、功耗低的特點;為了實現(xiàn)數(shù)字前端ASIC高精度數(shù)字位流輸出,給出了一種多位量化級聯(lián)結(jié)構(gòu)的數(shù)字sigma-delta調(diào)制器的設(shè)計,設(shè)計中采用誤差反饋結(jié)構(gòu),通過多級級聯(lián)實現(xiàn)高精度ASIC數(shù)字位流輸出,降低損耗;考慮到調(diào)制器多位數(shù)字量化技術(shù)易產(chǎn)生非線性問題,本文還進行了動態(tài)匹配單元設(shè)計,采用數(shù)字加權(quán)平均算法(DWA)將調(diào)制器輸出信號產(chǎn)生的失配噪聲轉(zhuǎn)化為白噪聲進而通過低通濾波器濾除。在Sigma-Delta DAC數(shù)字前端專用集成電路結(jié)構(gòu)實現(xiàn)方面,進行了多種技術(shù)的優(yōu)化。首先,基于采樣保持電路,對數(shù)字插值濾波器結(jié)構(gòu)進行優(yōu)化,為了進一步降低功耗,進行先濾波后插值結(jié)構(gòu)設(shè)計;在多位量化數(shù)字sigma-delta調(diào)制器硬件電路結(jié)構(gòu)設(shè)計方面,采用MASH1-1-1結(jié)構(gòu),每一級量化器都采用向下截位的方式進行實現(xiàn),通過使用移位方式進行乘法操作,以減小電路面積的消耗;在DWA算法硬件結(jié)構(gòu)實現(xiàn)時,基于溫度計碼,采用循環(huán)移位的方式來實現(xiàn);為了縮減輸入數(shù)據(jù)端口的數(shù)量,本文采用串口總線SPI接口,對電路的輸入數(shù)據(jù)進行串并轉(zhuǎn)換。最后,本文對整體數(shù)字前端專用集成電路進行了硬件實現(xiàn),采用Cadence Encounter工具,基于0.35μm CMOS工藝,進行了布局布線,時序優(yōu)化,完成了整體物理版圖的設(shè)計、后仿真,并進行了流片,所設(shè)計的芯片面積為3.0mm×2.8mm。采用FPGA對所設(shè)計整體電路進行了測試驗證。實驗結(jié)果表明,該數(shù)字前端專用集成電路信噪比約為143.5dB以上,有效位數(shù)約為23.5位。
[Abstract]:The digitization of micro-mechanical gyroscope is one of the hotspots in the field of inertial sensor system at present, and the digital micro-mechanical gyroscope system has gradually become the mainstream of design. In digital micromachined gyroscope system, high precision DAC is one of the key modules. In this paper, a high-precision sigma-delta DAC digital front-end integrated circuit (ASIC) design for MEMS gyroscope system is studied. This paper consists of three main modules: digital interpolation filter, sigma-delta modulator, DEM dynamic unit matching module. The digital interpolation filter is designed by cascading structure of multi-stage digital filter. The cascade structure includes two-stage half-band filter, CIC compensation filter and CIC filter. Based on the analysis of the traditional half-band filter, the digital interpolation filter consists of two-stage half-band filter, CIC compensation filter and CIC filter. A robust half-band filter structure is proposed, which improves the transfer function of the traditional half-band filter, and makes its amplitude-frequency characteristic less sensitive to the filter coefficients, and the structure has low consumption of hardware circuit. The circuit has the characteristics of high speed and low power consumption. In order to realize the high precision digital bit stream output of digital front-end ASIC, the design of a multi-bit quantized cascaded digital sigma-delta modulator is presented. The error feedback structure is used in the design, and the high-precision ASIC digital bit stream output is realized by multi-concatenation. Reduce loss; Considering the nonlinearity of the modulator multi-digit quantization technology, the dynamic matching unit is also designed in this paper. The digital weighted average (DWA) algorithm is used to transform the mismatch noise generated by the modulator's output signal into white noise and then filter it by low-pass filter. In the aspect of Sigma-Delta DAC digital front-end ASIC architecture, a variety of optimization techniques have been carried out. Firstly, the structure of the digital interpolation filter is optimized based on the sampling and holding circuit. In order to reduce the power consumption further, the filter structure is first filtered and then the interpolation structure is designed. In the design of hardware circuit structure of multi-bit quantized digital sigma-delta modulator, MASH1-1-1 structure is adopted, every first-level quantizer is implemented by way of downward truncation, and multiplicative operation is carried out by using shift mode. To reduce the consumption of circuit area; In order to reduce the number of input data ports, the serial bus SPI interface is used to convert the input data of the circuit to serial-parallel conversion, when the hardware structure of the DWA algorithm is implemented, which is based on the thermometer code and the way of cyclic shift, in order to reduce the number of input data ports. Finally, the hardware implementation of the integrated digital front-end ASIC is carried out. Based on the 0.35m CMOS process, the layout and routing of the integrated digital front-end ASIC is carried out by using the Cadence Encounter tool, and the timing optimization is carried out. The whole physical layout is designed, and the post-simulation is carried out. The chip area is 3.0mm 脳 2.8 mm. The whole circuit is tested and verified by FPGA. The experimental results show that the signal-to-noise ratio of the digital front-end ASIC is more than 143.5dB and the effective bit is about 23.5 bits.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TN792
本文編號：2447339
[Abstract]:The digitization of micro-mechanical gyroscope is one of the hotspots in the field of inertial sensor system at present, and the digital micro-mechanical gyroscope system has gradually become the mainstream of design. In digital micromachined gyroscope system, high precision DAC is one of the key modules. In this paper, a high-precision sigma-delta DAC digital front-end integrated circuit (ASIC) design for MEMS gyroscope system is studied. This paper consists of three main modules: digital interpolation filter, sigma-delta modulator, DEM dynamic unit matching module. The digital interpolation filter is designed by cascading structure of multi-stage digital filter. The cascade structure includes two-stage half-band filter, CIC compensation filter and CIC filter. Based on the analysis of the traditional half-band filter, the digital interpolation filter consists of two-stage half-band filter, CIC compensation filter and CIC filter. A robust half-band filter structure is proposed, which improves the transfer function of the traditional half-band filter, and makes its amplitude-frequency characteristic less sensitive to the filter coefficients, and the structure has low consumption of hardware circuit. The circuit has the characteristics of high speed and low power consumption. In order to realize the high precision digital bit stream output of digital front-end ASIC, the design of a multi-bit quantized cascaded digital sigma-delta modulator is presented. The error feedback structure is used in the design, and the high-precision ASIC digital bit stream output is realized by multi-concatenation. Reduce loss; Considering the nonlinearity of the modulator multi-digit quantization technology, the dynamic matching unit is also designed in this paper. The digital weighted average (DWA) algorithm is used to transform the mismatch noise generated by the modulator's output signal into white noise and then filter it by low-pass filter. In the aspect of Sigma-Delta DAC digital front-end ASIC architecture, a variety of optimization techniques have been carried out. Firstly, the structure of the digital interpolation filter is optimized based on the sampling and holding circuit. In order to reduce the power consumption further, the filter structure is first filtered and then the interpolation structure is designed. In the design of hardware circuit structure of multi-bit quantized digital sigma-delta modulator, MASH1-1-1 structure is adopted, every first-level quantizer is implemented by way of downward truncation, and multiplicative operation is carried out by using shift mode. To reduce the consumption of circuit area; In order to reduce the number of input data ports, the serial bus SPI interface is used to convert the input data of the circuit to serial-parallel conversion, when the hardware structure of the DWA algorithm is implemented, which is based on the thermometer code and the way of cyclic shift, in order to reduce the number of input data ports. Finally, the hardware implementation of the integrated digital front-end ASIC is carried out. Based on the 0.35m CMOS process, the layout and routing of the integrated digital front-end ASIC is carried out by using the Cadence Encounter tool, and the timing optimization is carried out. The whole physical layout is designed, and the post-simulation is carried out. The chip area is 3.0mm 脳 2.8 mm. The whole circuit is tested and verified by FPGA. The experimental results show that the signal-to-noise ratio of the digital front-end ASIC is more than 143.5dB and the effective bit is about 23.5 bits.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TN792
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