光刻友好型冗余金屬填充方法研究
發(fā)布時(shí)間：2019-03-25 18:00
【摘要】：隨著集成工藝節(jié)點(diǎn)的不斷進(jìn)步,由設(shè)計(jì)引起的產(chǎn)品良率下降成為了制約集成電路進(jìn)一步按摩爾定律發(fā)展的瓶頸。至此,設(shè)計(jì)與制造環(huán)節(jié)不再相互孤立,信息交互的重要性日益凸顯,可制造性設(shè)計(jì)(Design For Manufacture, DFM)技術(shù)應(yīng)運(yùn)而生。其中,冗余金屬填充技術(shù)利用無(wú)功能性的金屬圖形填充來(lái)控制互連層版圖圖形密度,是目前最廣泛采用的優(yōu)化化學(xué)機(jī)械拋光(Chemical-Mechanical Polishing, CMP)后芯片平坦度的可制造性設(shè)計(jì)方法。填充冗余金屬一方面由于引入寄生參數(shù)惡化了芯片的電學(xué)性能,影響了時(shí)序和功耗,另一方面,隨著特征尺寸的減小,光刻圖形尺寸已接近曝光系統(tǒng)的理論極限,冗余金屬的存在加劇了的原始版圖光刻圖形畸變,需要引起足夠的重視。本文在45nm的工藝條件下,針對(duì)冗余金屬填充引起的光學(xué)問(wèn)題做出研究,并提出優(yōu)化方案。1)對(duì)互連線端與線的位置關(guān)系建立模型,研究了互連圖形相對(duì)位置對(duì)光刻畸變的影響。2)針對(duì)特殊的T字型、Z字型、線端結(jié)構(gòu),分別設(shè)計(jì)了冗余金屬預(yù)填充方案,修復(fù)原始版圖中已存在的光刻熱點(diǎn)。3)設(shè)計(jì)了靈活、高效的光刻友好型冗余金屬填充流程,并應(yīng)用到設(shè)計(jì)實(shí)例中,減少冗余金屬引入的新光刻熱點(diǎn),實(shí)現(xiàn)了光刻與CMP后平坦度的平衡。研究結(jié)果表明,利用本文設(shè)計(jì)的光刻友好型冗余金屬填充流程,原始版圖特殊光刻熱點(diǎn)修復(fù)率可達(dá)41.47%,新產(chǎn)生的熱點(diǎn)數(shù)比普通填充降低了70.71%。其中,最小寬度檢查(Min Width Check, MWC)熱點(diǎn)修復(fù)率達(dá)到86.67%,新增的線端檢查(Line-End Check,LEC)熱點(diǎn)數(shù)僅為普通填充的1/4。此外,CMP后平坦度與普通填充持平,保證了冗余金屬對(duì)平坦度的優(yōu)化,且使最終的填充量降低了1.62%。
[Abstract]:With the continuous progress of integrated process nodes, the decline of product yield caused by design has become the bottleneck of further development of integrated circuits according to Moore's law. So far, design and manufacturing links are no longer isolated from each other, and the importance of information interaction is becoming more and more prominent. Manufacturable design (Design For Manufacture, DFM) technology emerges as the times require. Among them, redundant metal filling technology uses non-functional metal pattern filling to control the pattern density of interconnection layer, which is the most widely used optimization chemical mechanical polishing (Chemical-Mechanical Polishing,) at present. CMP) the design method of manufacturability for chip flatness. On the one hand, the introduction of parasitic parameters worsens the electrical performance of the chip, which affects the timing and power consumption. On the other hand, with the decrease of the feature size, the lithographic pattern size is close to the theoretical limit of the exposure system. The existence of redundant metal aggravates the distortion of the original lithography pattern, which needs to be paid more attention. In this paper, the optical problems caused by redundant metal filling are studied under the technological conditions of 45nm, and the optimization scheme is put forward. 1) the model of the relationship between the end of the interconnection and the position of the line is established. The influence of the relative position of the interconnection pattern on lithography distortion is studied. 2) for the special T-shape, Z-shape and line-end structure, the redundant metal pre-filling scheme is designed respectively. 3) flexible and efficient lithography-friendly redundant metal filling process is designed and applied to design examples to reduce the new lithographic hot spots introduced by redundant metals. The balance between lithography and post-CMP flatness is achieved. The results show that using the lithography-friendly redundant metal filling process designed in this paper, the repair rate of special lithographic hotspots in the original layout can reach 41.47%, and the newly generated hot spots are reduced by 70.71% compared with the ordinary ones. Among them, the minimum width check (Min Width Check, MWC) hot spot repair rate reached 86.67%, the new line-end check (Line-End Check,LEC) hot spot number is only 1-4% of the ordinary fill. In addition, the flatness after CMP is equal to that of ordinary filling, which ensures the optimization of flatness of redundant metals, and reduces the final filling amount by 1.62%.
【學(xué)位授予單位】：大連理工大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN405
本文編號(hào)：2447192
[Abstract]:With the continuous progress of integrated process nodes, the decline of product yield caused by design has become the bottleneck of further development of integrated circuits according to Moore's law. So far, design and manufacturing links are no longer isolated from each other, and the importance of information interaction is becoming more and more prominent. Manufacturable design (Design For Manufacture, DFM) technology emerges as the times require. Among them, redundant metal filling technology uses non-functional metal pattern filling to control the pattern density of interconnection layer, which is the most widely used optimization chemical mechanical polishing (Chemical-Mechanical Polishing,) at present. CMP) the design method of manufacturability for chip flatness. On the one hand, the introduction of parasitic parameters worsens the electrical performance of the chip, which affects the timing and power consumption. On the other hand, with the decrease of the feature size, the lithographic pattern size is close to the theoretical limit of the exposure system. The existence of redundant metal aggravates the distortion of the original lithography pattern, which needs to be paid more attention. In this paper, the optical problems caused by redundant metal filling are studied under the technological conditions of 45nm, and the optimization scheme is put forward. 1) the model of the relationship between the end of the interconnection and the position of the line is established. The influence of the relative position of the interconnection pattern on lithography distortion is studied. 2) for the special T-shape, Z-shape and line-end structure, the redundant metal pre-filling scheme is designed respectively. 3) flexible and efficient lithography-friendly redundant metal filling process is designed and applied to design examples to reduce the new lithographic hot spots introduced by redundant metals. The balance between lithography and post-CMP flatness is achieved. The results show that using the lithography-friendly redundant metal filling process designed in this paper, the repair rate of special lithographic hotspots in the original layout can reach 41.47%, and the newly generated hot spots are reduced by 70.71% compared with the ordinary ones. Among them, the minimum width check (Min Width Check, MWC) hot spot repair rate reached 86.67%, the new line-end check (Line-End Check,LEC) hot spot number is only 1-4% of the ordinary fill. In addition, the flatness after CMP is equal to that of ordinary filling, which ensures the optimization of flatness of redundant metals, and reduces the final filling amount by 1.62%.
【學(xué)位授予單位】：大連理工大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN405
【參考文獻(xiàn)】
相關(guān)期刊論文 前3條
1 阮文彪;陳嵐;李志剛;葉甜春;;Effects of pattern characteristics on copper CMP[J];半導(dǎo)體學(xué)報(bào);2009年04期
2 阮文彪;陳嵐;馬天宇;方晶晶;張賀;葉甜春;;Optimization of a Cu CMP process modeling parameters of nanometer integrated circuits[J];半導(dǎo)體學(xué)報(bào);2012年08期
3 賈艷明;蔡懿慈;洪先龍;;考慮性能優(yōu)化的冗余金屬填充算法[J];計(jì)算機(jī)輔助設(shè)計(jì)與圖形學(xué)學(xué)報(bào);2008年06期
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