3D-IC中TSV的冗余布局與可測(cè)性結(jié)構(gòu)優(yōu)化方法研究
發(fā)布時(shí)間：2019-03-16 11:57
【摘要】：隨著半導(dǎo)體技術(shù)的迅猛發(fā)展,集成芯片性能在摩爾定律的指導(dǎo)下不斷提高,尤其是近年來3D集成芯片技術(shù)的出現(xiàn)更是在一定意義上打破了摩爾定律,實(shí)現(xiàn)了更高層次的集成性能。隨著各大半導(dǎo)體公司逐步推出3D芯片系列產(chǎn)品,其測(cè)試方法引起學(xué)術(shù)界的廣泛關(guān)注。尤其是TSV穿透硅通孔(Through Silicon Via)的出現(xiàn),更引出了一系列測(cè)試問題,由于其成品率相對(duì)于現(xiàn)有的集成芯片技術(shù)較低,在測(cè)試方面更需要新的手段和技術(shù)。全文結(jié)構(gòu)采用由底層研究向頂層研究的結(jié)構(gòu),從TSV的失效機(jī)理入手,研究其失效和修復(fù),之后著眼于頂層整個(gè)3D-IC的可測(cè)性結(jié)構(gòu)的方向。本文主要介紹了3D集成芯片測(cè)試的一些關(guān)鍵性問題。第一,針對(duì)TSV的失效,研究在制造過程中由于工藝缺陷而造成的各種TSV失效機(jī)理,針對(duì)失效后TSV的電學(xué)外特性進(jìn)行RC電路的故障建模,運(yùn)用Hspice仿真工具模擬典型故障的充放電過程,給出了具體的故障電壓以及發(fā)生故障的位置不同引起的故障電壓偏差。第二,針對(duì)TSV的硬故障設(shè)計(jì)TSV冗余結(jié)構(gòu),根據(jù)此冗余切換結(jié)構(gòu)的特性進(jìn)行區(qū)塊內(nèi)部的冗余TSV的數(shù)量分析,修復(fù)率分析以及成品率分析等等。并且在面積開銷及時(shí)間開銷等方面綜合評(píng)價(jià)TSV冗余結(jié)構(gòu)。通過TSV冗余數(shù)量和修復(fù)率對(duì)冗余結(jié)構(gòu)進(jìn)行綜合分析,芯片成品率與冗余TSV數(shù)量直接相關(guān),本文方法在面積和時(shí)間開銷方面均有降低,結(jié)果表明這種TSV冗余結(jié)構(gòu)能夠覆蓋絕大多數(shù)TSV故障并且將成品率提高到99%,這能夠有效的降低成本。第三,針對(duì)測(cè)試結(jié)構(gòu)及對(duì)應(yīng)測(cè)試訪問機(jī)制的優(yōu)化,在前期研究中仿真實(shí)現(xiàn)了串行測(cè)試和并行測(cè)試兩種結(jié)構(gòu)后,綜合考慮這兩種測(cè)試方法的優(yōu)點(diǎn),在測(cè)試時(shí)間、硬件冗余、測(cè)試帶寬和功耗示蹤的溫度四種條件限制下,以得到最小的測(cè)試負(fù)擔(dān)系數(shù)為目標(biāo),對(duì)測(cè)試訪問機(jī)制進(jìn)行一種基于ILP思想的綜合優(yōu)化,即實(shí)現(xiàn)了基于混合封裝策略的Df T設(shè)計(jì),實(shí)驗(yàn)結(jié)果表明,該方法能夠得到較小的測(cè)試負(fù)擔(dān)系數(shù),為測(cè)試訪問機(jī)制的優(yōu)化設(shè)計(jì)提供參考。
[Abstract]:With the rapid development of semiconductor technology, the performance of integrated chips has been improved under the guidance of Moore's law, especially in recent years, the appearance of 3D integrated chip technology has broken Moore's law in a certain sense. A higher level of integration performance is achieved. With the introduction of three-dimensional chip series by semiconductor companies, the testing methods have attracted wide attention in academia. Especially, the emergence of TSV through silicon-through-hole (Through Silicon Via) leads to a series of testing problems. Because of its low yield compared with the existing integrated chip technology, it needs more new methods and techniques in the field of testing. Based on the failure mechanism of TSV, the failure and repair of the full-text structure is studied, and then the direction of the testability structure of the whole top-level 3D-IC is focused on. This paper mainly introduces some key problems of 3D integrated chip testing. Firstly, aiming at the failure of TSV, the failure mechanism of TSV due to process defects in manufacturing process is studied, and the fault modeling of RC circuit is carried out according to the external electrical characteristics of TSV after failure. The charge-discharge process of typical fault is simulated by using Hspice simulation tool. The specific fault voltage and the fault voltage deviation caused by different fault location are given. Secondly, the redundancy structure of TSV is designed for the hard fault of TSV. According to the characteristics of the redundant switching structure, the quantity analysis, repair rate analysis and yield analysis of the redundant TSV within the block are carried out. At the same time, the redundancy structure of TSV is comprehensively evaluated in the aspects of area cost and time cost. The redundant structure is analyzed by the number of redundant TSV and the repair rate. The chip yield is directly related to the number of redundant TSV. The method in this paper has reduced both area and time overhead, and the chip yield is directly related to the number of redundant TSV. The results show that the TSV redundancy structure can cover the majority of TSV faults and increase the yield to 99%, which can effectively reduce the cost. Thirdly, aiming at the optimization of the test structure and the corresponding test access mechanism, after the serial test and parallel test are simulated and implemented in the previous research, the advantages of these two testing methods are considered comprehensively, such as test time, hardware redundancy, and so on. Under the four conditions of test bandwidth and power tracer temperature, in order to obtain the minimum test burden coefficient, a comprehensive optimization of test access mechanism based on ILP idea is carried out, that is, the design of Df T based on hybrid encapsulation strategy is realized. The experimental results show that the proposed method can obtain a small test burden coefficient, which provides a reference for the optimization design of the test access mechanism.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN407
本文編號(hào)：2441308
[Abstract]:With the rapid development of semiconductor technology, the performance of integrated chips has been improved under the guidance of Moore's law, especially in recent years, the appearance of 3D integrated chip technology has broken Moore's law in a certain sense. A higher level of integration performance is achieved. With the introduction of three-dimensional chip series by semiconductor companies, the testing methods have attracted wide attention in academia. Especially, the emergence of TSV through silicon-through-hole (Through Silicon Via) leads to a series of testing problems. Because of its low yield compared with the existing integrated chip technology, it needs more new methods and techniques in the field of testing. Based on the failure mechanism of TSV, the failure and repair of the full-text structure is studied, and then the direction of the testability structure of the whole top-level 3D-IC is focused on. This paper mainly introduces some key problems of 3D integrated chip testing. Firstly, aiming at the failure of TSV, the failure mechanism of TSV due to process defects in manufacturing process is studied, and the fault modeling of RC circuit is carried out according to the external electrical characteristics of TSV after failure. The charge-discharge process of typical fault is simulated by using Hspice simulation tool. The specific fault voltage and the fault voltage deviation caused by different fault location are given. Secondly, the redundancy structure of TSV is designed for the hard fault of TSV. According to the characteristics of the redundant switching structure, the quantity analysis, repair rate analysis and yield analysis of the redundant TSV within the block are carried out. At the same time, the redundancy structure of TSV is comprehensively evaluated in the aspects of area cost and time cost. The redundant structure is analyzed by the number of redundant TSV and the repair rate. The chip yield is directly related to the number of redundant TSV. The method in this paper has reduced both area and time overhead, and the chip yield is directly related to the number of redundant TSV. The results show that the TSV redundancy structure can cover the majority of TSV faults and increase the yield to 99%, which can effectively reduce the cost. Thirdly, aiming at the optimization of the test structure and the corresponding test access mechanism, after the serial test and parallel test are simulated and implemented in the previous research, the advantages of these two testing methods are considered comprehensively, such as test time, hardware redundancy, and so on. Under the four conditions of test bandwidth and power tracer temperature, in order to obtain the minimum test burden coefficient, a comprehensive optimization of test access mechanism based on ILP idea is carried out, that is, the design of Df T based on hybrid encapsulation strategy is realized. The experimental results show that the proposed method can obtain a small test burden coefficient, which provides a reference for the optimization design of the test access mechanism.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN407
【參考文獻(xiàn)】
相關(guān)碩士學(xué)位論文 前1條
1 楊年宏;基于三維結(jié)構(gòu)的SoC低功耗測(cè)試技術(shù)研究[D];合肥工業(yè)大學(xué);2011年
，本文編號(hào)：2441308
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