P-i-N 二極管雪崩耐量測試過程的仿真分析與機(jī)理研究
發(fā)布時間：2019-02-16 22:08
【摘要】：功率快恢復(fù)二極管(Fast Recovery Diode,FRD)常與全控型開關(guān)器件反并聯(lián)構(gòu)成完整的開關(guān)模塊,在電路開關(guān)過程中起提供回路能量泄放的作用,防止感性負(fù)載回路硬關(guān)斷時產(chǎn)生危險的過電壓。正因?yàn)槿绱?二極管常常因?yàn)槲者^大的能量而導(dǎo)致?lián)p毀,其雪崩耐量將極大影響整個電路甚至系統(tǒng)的正常工作及堅(jiān)固性,因此針對功率FRD在該類應(yīng)用中的雪崩耐量問題進(jìn)行深入研究十分迫切。對功率器件的雪崩能力評價一般是在非鉗位感性開關(guān)(Unclamped Inductive Load Switching,UIS)條件下測量,目前國際上關(guān)于功率FRD的雪崩耐量的文獻(xiàn)非常稀少,更未見到有系統(tǒng)研究的報(bào)道。本文重點(diǎn)利用器件仿真工具以P-i-N二極管為模型對其雪崩耐量測試過程中內(nèi)部物理量的演變過程及機(jī)理進(jìn)行探討和分析,試圖為FRD提高雪崩耐量設(shè)計(jì)提供基本的物理理解、基礎(chǔ)數(shù)據(jù)和方向指導(dǎo)。采用分段線性電流源激勵模擬UIS電路中開關(guān)瞬間關(guān)斷時P-i-N二極管受到的電流沖擊,利用Sentaurus TCAD仿真軟件進(jìn)行熱電耦合的瞬態(tài)仿真分析,針對一個耐壓為350V左右具有p+n-n+結(jié)構(gòu)及場板型結(jié)終端的參考結(jié)構(gòu)以EAS=1.3mJ的能量進(jìn)行沖擊,發(fā)現(xiàn)在雪崩耐量測試過程中,器件外端電壓主要經(jīng)歷了過沖、負(fù)阻及振蕩、周期性發(fā)展三個階段。從負(fù)阻階段開始,在p+n-結(jié)及n-n+結(jié)處都發(fā)生了局部的雪崩注入,出現(xiàn)了電流集中現(xiàn)象,形成的電流絲位于結(jié)邊緣處,寬度約10um,峰值電流密度3.3×104A/cm2。峰值溫度曲線的周期性變化與電流絲的運(yùn)動同步,表現(xiàn)為電流絲運(yùn)動到左右邊緣停留時對應(yīng)溫度的迅速尖峰化,尖峰值平均每次升高80K,而電流絲平移過程對應(yīng)峰值溫度的降落。分析其中機(jī)理可知電流絲的運(yùn)動源于電流絲的自熱效應(yīng)和碰撞電離率的負(fù)溫度系數(shù)。隨后,通過增大雪崩耐量測試能量EAS,以峰值溫度升高到800K作為失效點(diǎn),預(yù)測了可能發(fā)生的失效位置始終為主結(jié)邊緣處。通過添加單浮場環(huán)發(fā)現(xiàn)盡管使電場集中位置移到場環(huán)邊緣,但失效位置仍位于主結(jié),實(shí)測結(jié)果與仿真預(yù)測一致。最后,對P-i-N二極管的靜電放電(Electrostatic Discharge,ESD)過程進(jìn)行了仿真計(jì)算,討論了雪崩耐量測試和反偏ESD測試過程的共性和差異,這些發(fā)現(xiàn)及其他相關(guān)仿真結(jié)果對后續(xù)提高FRD雪崩耐量及抗ESD能力的研究將有重要的參考意義。
[Abstract]:The power fast recovery diode (Fast Recovery Diode,FRD) often forms a complete switch module in reverse parallel with the full control switch device, which can provide the circuit with the function of releasing the energy of the circuit during the switching process. Prevent dangerous overvoltage when the inductive load loop is hard turned off. Because of this, diodes are often damaged by absorbing too much energy, and their avalanche tolerance will greatly affect the normal functioning and robustness of the entire circuit and even the system. Therefore, it is very urgent to study the avalanche tolerance problem of power FRD in this kind of applications. The evaluation of the avalanche capability of power devices is generally measured under the condition of non-clamped inductive switch (Unclamped Inductive Load Switching,UIS). At present, there is very little literature on the avalanche tolerance of power FRD in the world, and no systematic research has been reported. In this paper, the evolvement process and mechanism of internal physical quantities in the process of avalanche tolerance testing are discussed and analyzed by using the device simulation tool with P-i-N diode as the model. This paper attempts to provide basic physical understanding, basic data and direction guidance for FRD to improve avalanche tolerance design. A piecewise linear current source is used to simulate the current shock of the P-i-N diode when the switch is switched off in the UIS circuit, and the transient simulation analysis of thermoelectric coupling is carried out by using the Sentaurus TCAD simulation software. For a reference structure with a voltage of 350V or so with a p-n-n structure and a field-plate junction terminal, the energy of EAS=1.3mJ is used to impact. It is found that in the process of avalanche tolerance measurement, the external terminal voltage of the device mainly undergoes overshoot, negative resistance and oscillation. Three stages of periodic development. From the negative resistance stage, the local avalanche injection occurs at both p-n- and n-n junctions, and the current concentration occurs. The resulting current filament is located at the edge of the junction, the width is about 10 umps, and the peak current density is 3.3 脳 104A / cm ~ (2). The periodic variation of the peak temperature curve synchronizes with the current wire movement, which shows that the current wire moves to the left and right edges of the wire, which corresponds to the rapid peak of the temperature. The peak value of the current wire increases by an average of 80K each time. The current-wire translation process corresponds to the drop of peak temperature. It is found that the motion of the current wire originates from the self-heating effect of the current wire and the negative temperature coefficient of the collision ionization rate. Then, by increasing the avalanche tolerance test energy EAS, the peak temperature is increased to 800K as the failure point, and the possible failure position is always predicted at the edge of the junction. It is found by adding a single floating field ring that the failure position is still located in the main junction although the electric field concentration is moved to the edge of the ring. The measured results are in agreement with the simulation prediction. Finally, the electrostatic discharge (Electrostatic Discharge,ESD) process of P-i-N diode is simulated, and the generality and difference of avalanche tolerance test and reverse bias ESD test are discussed. These findings and other relevant simulation results will be of great significance for further research on improving FRD avalanche tolerance and ESD resistance.
【學(xué)位授予單位】：北京工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN312.4
本文編號：2424883
[Abstract]:The power fast recovery diode (Fast Recovery Diode,FRD) often forms a complete switch module in reverse parallel with the full control switch device, which can provide the circuit with the function of releasing the energy of the circuit during the switching process. Prevent dangerous overvoltage when the inductive load loop is hard turned off. Because of this, diodes are often damaged by absorbing too much energy, and their avalanche tolerance will greatly affect the normal functioning and robustness of the entire circuit and even the system. Therefore, it is very urgent to study the avalanche tolerance problem of power FRD in this kind of applications. The evaluation of the avalanche capability of power devices is generally measured under the condition of non-clamped inductive switch (Unclamped Inductive Load Switching,UIS). At present, there is very little literature on the avalanche tolerance of power FRD in the world, and no systematic research has been reported. In this paper, the evolvement process and mechanism of internal physical quantities in the process of avalanche tolerance testing are discussed and analyzed by using the device simulation tool with P-i-N diode as the model. This paper attempts to provide basic physical understanding, basic data and direction guidance for FRD to improve avalanche tolerance design. A piecewise linear current source is used to simulate the current shock of the P-i-N diode when the switch is switched off in the UIS circuit, and the transient simulation analysis of thermoelectric coupling is carried out by using the Sentaurus TCAD simulation software. For a reference structure with a voltage of 350V or so with a p-n-n structure and a field-plate junction terminal, the energy of EAS=1.3mJ is used to impact. It is found that in the process of avalanche tolerance measurement, the external terminal voltage of the device mainly undergoes overshoot, negative resistance and oscillation. Three stages of periodic development. From the negative resistance stage, the local avalanche injection occurs at both p-n- and n-n junctions, and the current concentration occurs. The resulting current filament is located at the edge of the junction, the width is about 10 umps, and the peak current density is 3.3 脳 104A / cm ~ (2). The periodic variation of the peak temperature curve synchronizes with the current wire movement, which shows that the current wire moves to the left and right edges of the wire, which corresponds to the rapid peak of the temperature. The peak value of the current wire increases by an average of 80K each time. The current-wire translation process corresponds to the drop of peak temperature. It is found that the motion of the current wire originates from the self-heating effect of the current wire and the negative temperature coefficient of the collision ionization rate. Then, by increasing the avalanche tolerance test energy EAS, the peak temperature is increased to 800K as the failure point, and the possible failure position is always predicted at the edge of the junction. It is found by adding a single floating field ring that the failure position is still located in the main junction although the electric field concentration is moved to the edge of the ring. The measured results are in agreement with the simulation prediction. Finally, the electrostatic discharge (Electrostatic Discharge,ESD) process of P-i-N diode is simulated, and the generality and difference of avalanche tolerance test and reverse bias ESD test are discussed. These findings and other relevant simulation results will be of great significance for further research on improving FRD avalanche tolerance and ESD resistance.
【學(xué)位授予單位】：北京工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN312.4
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，本文編號：2424883
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