電力線載波芯片數(shù)字后端設(shè)計(jì)
發(fā)布時(shí)間：2019-02-13 08:26
【摘要】：電力線作為一種現(xiàn)代社會(huì)基礎(chǔ)設(shè)施,分布范圍極廣。智能電表以電力線作為載波介質(zhì),受到國(guó)內(nèi)外高度重視。電力線載波(Power Line Carrier,PLC)芯片是智能電表的核心部件。本文對(duì)一種具有可擴(kuò)展射頻收發(fā)功能的新型電力線載波芯片BES3803進(jìn)行了研究,主要工作如下:1.基于SMIC 0.18μm mixed signal工藝,使用Design Compiler工具對(duì)芯片進(jìn)行了帶有可測(cè)試性設(shè)計(jì)的邏輯綜合,將電力線載波芯片用門級(jí)電路實(shí)現(xiàn),同時(shí)將電路中的時(shí)序器件替換為具有可測(cè)試性端口的器件,并針對(duì)儲(chǔ)存器插入自建內(nèi)測(cè)試電路,以供流片后測(cè)試用。使用Prime Time工具對(duì)邏輯綜合生成的門級(jí)網(wǎng)表進(jìn)行了時(shí)序分析,再用Formality工具對(duì)RTL級(jí)代碼和生成的門級(jí)網(wǎng)表進(jìn)行形式驗(yàn)證,保證了邏輯綜合的正確性。2.基于SMIC 0.18μm mixed signal工藝,使用Astro工具實(shí)現(xiàn)了芯片物理版圖設(shè)計(jì)。包括:布局規(guī)劃、時(shí)鐘樹(shù)綜合、布線、寄生參數(shù)提取、時(shí)序分析、物理驗(yàn)證和形式驗(yàn)證。在布局規(guī)劃中,采用一種模塊限定布局、電源網(wǎng)絡(luò)線寬優(yōu)化相結(jié)合的非均勻階梯型電源網(wǎng)絡(luò)優(yōu)化方法對(duì)數(shù)字模塊電源網(wǎng)絡(luò)進(jìn)行改善,釋放了芯片繞線空間,減小了芯片面積,優(yōu)化了芯片功耗。在時(shí)鐘樹(shù)綜合中,采用一種忽略門控時(shí)鐘偏移檢查的新型時(shí)鐘樹(shù)綜合、局部時(shí)鐘樹(shù)構(gòu)建的方法進(jìn)行優(yōu)化,大幅度減少了時(shí)鐘緩沖器插入數(shù)目,再次優(yōu)化了芯片功耗,減小了芯片面積。3.對(duì)芯片功能、功耗和電壓降進(jìn)行了仿真驗(yàn)證。結(jié)果表明,電力線載波芯片功能正確。針對(duì)芯片擴(kuò)展功能,進(jìn)行了匹配設(shè)計(jì)。本文設(shè)計(jì)的電力線載波芯片BES3803完成了芯片從RTL(register-transfer level)到GDSII(graphic design system II)的所有設(shè)計(jì)工作,最終芯片面積5.87mm2,功耗61.116mW,測(cè)試覆蓋率98.21%。仿真驗(yàn)證表明,芯片功能正常,且相比原有芯片性能大幅度提高,功能更加強(qiáng)大,具有更強(qiáng)的市場(chǎng)競(jìng)爭(zhēng)力。
[Abstract]:As a modern social infrastructure, power line is widely distributed. The intelligent ammeter takes the power line as the carrier medium, which is highly valued at home and abroad. Power line carrier (Power Line Carrier,PLC (PLC) chip is the core component of intelligent ammeter. In this paper, a new power line carrier chip BES3803 with extensible RF transceiver is studied. The main work is as follows: 1. Based on the SMIC 0.18 渭 m mixed signal technology, the logic synthesis of the chip with testability design is carried out by using the Design Compiler tool, and the power line carrier chip is realized by the gate circuit. At the same time, the sequential device in the circuit is replaced by the device with testability port, and the self-built test circuit is inserted for the memory to be used for the post-test of the chip. The sequential analysis of gate network table generated by logic synthesis is carried out by using Prime Time tool, and the formal verification of RTL level code and gate network table generated by Formality tool is carried out, which ensures the correctness of logic synthesis. 2. Based on SMIC 0.18 渭 m mixed signal process, the chip physical layout design is realized by using Astro tool. Including: layout planning, clock tree synthesis, routing, parasitic parameter extraction, timing analysis, physical verification and formal verification. In the layout planning, a non-uniform ladder power network optimization method is used to improve the digital module power network, which is designed to limit the layout and optimize the line width of the power supply network, thus freeing the chip winding space and reducing the chip area. The chip power consumption is optimized. In the clock tree synthesis, a new clock tree synthesis method, which ignores the gated clock offset check, is used to optimize the local clock tree construction, which greatly reduces the number of clock buffer inserts and optimizes the chip power consumption. Reduced chip area. 3. The function, power consumption and voltage drop of the chip are simulated and verified. The results show that the power line carrier chip functions correctly. According to the extended function of the chip, the matching design is carried out. The power line carrier chip BES3803 designed in this paper has completed all the design work from RTL (register-transfer level) to GDSII (graphic design system II). Finally, the chip area is 5.87mm-2, the power consumption is 61.116mW, and the test coverage is 98.21mW. The simulation results show that the chip has normal function, and compared with the original chip, the performance of the chip is greatly improved, the function is more powerful, and the chip has stronger market competitiveness.
【學(xué)位授予單位】：北京工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN402
本文編號(hào)：2421361
[Abstract]:As a modern social infrastructure, power line is widely distributed. The intelligent ammeter takes the power line as the carrier medium, which is highly valued at home and abroad. Power line carrier (Power Line Carrier,PLC (PLC) chip is the core component of intelligent ammeter. In this paper, a new power line carrier chip BES3803 with extensible RF transceiver is studied. The main work is as follows: 1. Based on the SMIC 0.18 渭 m mixed signal technology, the logic synthesis of the chip with testability design is carried out by using the Design Compiler tool, and the power line carrier chip is realized by the gate circuit. At the same time, the sequential device in the circuit is replaced by the device with testability port, and the self-built test circuit is inserted for the memory to be used for the post-test of the chip. The sequential analysis of gate network table generated by logic synthesis is carried out by using Prime Time tool, and the formal verification of RTL level code and gate network table generated by Formality tool is carried out, which ensures the correctness of logic synthesis. 2. Based on SMIC 0.18 渭 m mixed signal process, the chip physical layout design is realized by using Astro tool. Including: layout planning, clock tree synthesis, routing, parasitic parameter extraction, timing analysis, physical verification and formal verification. In the layout planning, a non-uniform ladder power network optimization method is used to improve the digital module power network, which is designed to limit the layout and optimize the line width of the power supply network, thus freeing the chip winding space and reducing the chip area. The chip power consumption is optimized. In the clock tree synthesis, a new clock tree synthesis method, which ignores the gated clock offset check, is used to optimize the local clock tree construction, which greatly reduces the number of clock buffer inserts and optimizes the chip power consumption. Reduced chip area. 3. The function, power consumption and voltage drop of the chip are simulated and verified. The results show that the power line carrier chip functions correctly. According to the extended function of the chip, the matching design is carried out. The power line carrier chip BES3803 designed in this paper has completed all the design work from RTL (register-transfer level) to GDSII (graphic design system II). Finally, the chip area is 5.87mm-2, the power consumption is 61.116mW, and the test coverage is 98.21mW. The simulation results show that the chip has normal function, and compared with the original chip, the performance of the chip is greatly improved, the function is more powerful, and the chip has stronger market competitiveness.
【學(xué)位授予單位】：北京工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN402
【參考文獻(xiàn)】
相關(guān)期刊論文 前1條
1 楊兵;張玲;魏敬和;于宗光;;ULSI后端設(shè)計(jì)低功耗技術(shù)研究[J];微電子學(xué);2014年01期
相關(guān)碩士學(xué)位論文 前1條
1 崔慶博;電路中電源/地網(wǎng)絡(luò)的優(yōu)化研究[D];北京交通大學(xué);2010年
，本文編號(hào)：2421361
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