【摘要】：隨著現(xiàn)代科技的發(fā)展,植入式生物醫(yī)療設(shè)備已成為熱點(diǎn)研究方向之一,相比于傳統(tǒng)便攜式醫(yī)療設(shè)備更具靈活性,對(duì)于疾病的診治有十分重要的意義。然而,如何使植入式醫(yī)療設(shè)備更為安全、穩(wěn)定地造�；颊�,仍面臨巨大的挑戰(zhàn),尤其對(duì)于植入式芯片,不僅其外形和尺寸受到解剖部位的限制,芯片工作時(shí)的功耗散熱也會(huì)損傷解剖部位的機(jī)體組織。逐次逼近(SAR:Successive-Approximation-Register)模/數(shù)轉(zhuǎn)換器(ADC: Analog-to-Digital Converter)具有結(jié)構(gòu)簡單、面積小、功耗低等特點(diǎn),廣泛應(yīng)用于生物醫(yī)療電子領(lǐng)域。本文針對(duì)植入式生物芯片應(yīng)用,重點(diǎn)對(duì)SAR ADC進(jìn)行功耗與面積優(yōu)化,完成電路設(shè)計(jì)、版圖設(shè)計(jì)及仿真驗(yàn)證。本文設(shè)計(jì)了一種10-bit低功耗SAR ADC,主要由采樣/保持電路、D/A轉(zhuǎn)換網(wǎng)絡(luò)、比較器以及SAR邏輯控制電路構(gòu)成。通過研究各模塊的不同電路結(jié)構(gòu)、探討影響電路性能的非理想因素,對(duì)傳統(tǒng)的電荷再分配型SAR ADC電路進(jìn)行了改進(jìn)及優(yōu)化,設(shè)計(jì)結(jié)果滿足了植入式生物芯片的低功耗要求。主要采取的設(shè)計(jì)方案包括：1.由于電容陣列不消耗靜態(tài)功耗,電荷再分配結(jié)構(gòu)是低功耗SAR ADC的主要結(jié)構(gòu),本文在分析目前已有的電容陣列結(jié)構(gòu)及開關(guān)時(shí)序的基礎(chǔ)上,提出了一種基于分段電容陣列的新型D/A轉(zhuǎn)換網(wǎng)絡(luò)及開關(guān)時(shí)序,重點(diǎn)改進(jìn)了分段電容陣列中冗余電容的結(jié)構(gòu),與目前已有的D/A轉(zhuǎn)換網(wǎng)絡(luò)相比,有效地降低了功耗與面積。2.本文設(shè)計(jì)的SAR ADC采用基于上極板采樣的差分輸入結(jié)構(gòu),一方面差分輸入結(jié)構(gòu)能夠很好地抑制共模干擾、提高ADC的性能,另外上極板采樣有效減小了輸入電容陣列的規(guī)模,利于功耗和面積優(yōu)化。3.在其它模塊電路方面,采樣/保持部分采用自舉式開關(guān)對(duì)輸入模擬信號(hào)進(jìn)行采樣,其相對(duì)恒定的導(dǎo)通電阻保證了采樣電路的線性度；本文設(shè)計(jì)的SAR ADC比較器采用兩級(jí)級(jí)聯(lián)的動(dòng)態(tài)結(jié)構(gòu),有效減小了整個(gè)ADC的靜態(tài)功耗；SAR邏輯控制部分采用由動(dòng)態(tài)單元組成的電路,很大程度上減小了邏輯電路的復(fù)雜度,降低了數(shù)字電路的功耗和面積。整個(gè)10-bit SAR ADC采用65nm CMOS工藝設(shè)計(jì)實(shí)現(xiàn),利用Cadence和Matlab工具進(jìn)行設(shè)計(jì)及仿真驗(yàn)證。在電源電壓與基準(zhǔn)電壓為0.8V,采樣速率為50KS/s,輸入為1.5KHz差分正弦信號(hào)時(shí),整個(gè)SAR ADC的信噪失真比(SNDR：Signal-to-Noise-and-Distortion Ratio)為61.42dB,有效位數(shù)(ENOB:Effective Number of Bits)為9.91,功耗為423nW,品質(zhì)因數(shù)(FoM:Figure of Merit)為8.7fJ/Conv. step。本文設(shè)計(jì)的SAR ADC版圖面積為136μm×176μm,非常適合植入式生物芯片應(yīng)用。
[Abstract]:With the development of modern science and technology, implantable biomedical devices have become one of the hot research directions. Compared with the traditional portable medical equipment, it is more flexible and has a very important significance for the diagnosis and treatment of diseases. However, how to make implantable medical devices safer and more stable for the benefit of patients still faces enormous challenges, especially for implanted chips, not only in terms of their shape and size, but also because of their anatomical location. The power dissipation of the chip can also damage the anatomical tissue. Successive approximation (SAR:Successive-Approximation-Register) A / D converter (ADC: Analog-to-Digital Converter) is widely used in biomedical electronics due to its simple structure, small area and low power consumption. This paper focuses on the optimization of power consumption and area of SAR ADC, circuit design, layout design and simulation verification for implanted biochip applications. In this paper, a low power 10-bit SAR ADC, is designed, which consists of a sampling / holding circuit, a D / A conversion network, a comparator and a SAR logic control circuit. By studying the different circuit structure of each module and discussing the non-ideal factors that affect the circuit performance, the traditional charge redistribution SAR ADC circuit is improved and optimized. The design results meet the low power requirement of implanted biochip. The main design projects are as follows: 1. Because capacitance array does not consume static power, charge redistribution structure is the main structure of low power SAR ADC. A novel D / A conversion network based on piecewise capacitor array and its switching timing are proposed. The structure of redundant capacitors in piecewise capacitor array is mainly improved, compared with the existing D / A conversion network. Effectively reduced power consumption and area. 2. The SAR ADC designed in this paper adopts differential input structure based on the sampling of upper pole plate. On the one hand, the differential input structure can suppress common-mode interference and improve the performance of ADC. On the other hand, the sampling of upper pole plate can effectively reduce the size of input capacitor array. Conducive to power consumption and area optimization. 3. In other module circuits, the sampling / holding part uses bootstrap switch to sample the input analog signal, and its relatively constant on-resistance ensures the linearity of the sampling circuit. The SAR ADC comparator designed in this paper adopts a two-stage cascade dynamic structure, which effectively reduces the static power consumption of the whole ADC. The logic control part of SAR uses a circuit composed of dynamic cells, which greatly reduces the complexity of the logic circuit and reduces the power consumption and area of the digital circuit. The whole 10-bit SAR ADC is realized by 65nm CMOS process design, and is designed and verified by Cadence and Matlab tools. When the supply voltage and reference voltage are 0.8V, the sampling rate is 50KS / s and the input is 1.5KHz differential sinusoidal signal, the signal to noise distortion ratio (SNDR:Signal-to-Noise-and-Distortion Ratio) of the whole SAR ADC is 61.42 dB. The number of significant bits (ENOB:Effective Number of Bits) is 9.91, power consumption is 423nW, FoM:Figure of Merit) is 8.7 fJ / Conv. Step. The SAR ADC area designed in this paper is 136 渭 m 脳 176 渭 m, which is very suitable for biochip implantation.
【學(xué)位授予單位】：西安郵電大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2016
【分類號(hào)】：TN792

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