【摘要】：隨著半導(dǎo)體工藝的日趨成熟,超大規(guī)模集成電路迅猛發(fā)展。但傳統(tǒng)的單核處理器性能,與當(dāng)前亟待研究的計(jì)算密集型應(yīng)用需求,如核能開發(fā)、宇宙空間探索,以及炙手可熱的人工智能,仍存在不可逾越的鴻溝。因此,計(jì)算機(jī)體系結(jié)構(gòu)逐漸由單核向多核、眾核、多片發(fā)展。以Intel為代表的同構(gòu)多核、多片系統(tǒng)與以NVIDIA為代表的異構(gòu)多核、多片系統(tǒng),逐漸成為芯片設(shè)計(jì)的必然趨勢(shì)。在此背景下,如何準(zhǔn)確、高效地傳輸數(shù)據(jù),成為多核、多片系統(tǒng)中至關(guān)重要的技術(shù)重心與設(shè)計(jì)難點(diǎn)。片間互聯(lián)接口協(xié)議主要有兩種:支持路由功能的胖樹結(jié)構(gòu)協(xié)議,與不支持路由功能的全互聯(lián)結(jié)構(gòu)協(xié)議。當(dāng)計(jì)算處理器核數(shù)小于8時(shí),由于胖樹結(jié)構(gòu)協(xié)議控制模塊設(shè)計(jì)復(fù)雜,多核之間需要交換機(jī)進(jìn)行數(shù)據(jù)轉(zhuǎn)發(fā),所以互聯(lián)結(jié)構(gòu)占用的面積與功耗較大。片間互聯(lián)的實(shí)現(xiàn)技術(shù)主要包含兩種:串行技術(shù)和并行技術(shù)。但隨著芯片面積逐漸減小,并行互聯(lián)技術(shù)中,互聯(lián)線間實(shí)現(xiàn)物理絕緣難度加大,時(shí)鐘偏差與信號(hào)串?dāng)_也日趨嚴(yán)重,此外,該技術(shù)需要占用芯片大量的引腳數(shù),增大了封裝難度與成本,降低了可靠性。因此,一種高效、可靠的全互聯(lián)串行互聯(lián)接口協(xié)議對(duì)于多片架構(gòu)設(shè)計(jì)具有十分重要的意義。針對(duì)應(yīng)用領(lǐng)域?qū)ζg互聯(lián)接口實(shí)時(shí)性和高帶寬的需求,本文深入調(diào)研現(xiàn)有的互聯(lián)協(xié)議,提出一種基于“包”,具備低延遲、高帶寬以及高擴(kuò)展性的全互聯(lián)串行互聯(lián)接口協(xié)議SLink。該協(xié)議由事務(wù)層、數(shù)據(jù)鏈路層和物理層三個(gè)部分組成。協(xié)議“包”格式簡(jiǎn)潔,選擇LVDS技術(shù)作為物理層的數(shù)據(jù)傳輸基礎(chǔ),支持可配置的CRC校驗(yàn)和硬件檢測(cè)重傳機(jī)制�；赟Link協(xié)議定義,提出一種實(shí)現(xiàn)方案,給出仿真評(píng)估數(shù)據(jù)及FPGA的驗(yàn)證結(jié)果。實(shí)驗(yàn)結(jié)果說明,相比PCI-Express 2.0接口,SLink接口傳輸延時(shí)平均減少61.0%,有效帶寬平均增加55.6%,控制器所占面積減小約97.5%。
[Abstract]:With the development of semiconductor technology, VLSI is developing rapidly. However, there is still an insurmountable gap between the performance of traditional single-core processors and the needs of computational intensive applications, such as nuclear energy development, space exploration, and the hot artificial intelligence. Therefore, the computer architecture is gradually developing from single core to multi-core, multi-core and multi-chip. Isomorphic multicore, multi-chip system represented by Intel and heterogeneous multi-core and multi-chip system represented by NVIDIA are becoming the inevitable trend of chip design. Under this background, how to transmit data accurately and efficiently becomes the most important technical center of gravity and design difficulty in multi-core and multi-chip system. There are two kinds of inter-chip interfacing protocols: fat tree protocol which supports routing function and full interconnection protocol which does not support routing function. When the number of processor cores is less than 8, due to the complexity of the design of the protocol control module of the fat-tree structure and the need for the switch to transmit the data between the multi-cores, the area and power consumption of the interconnected architecture are large. The realization technology of interchip interconnection mainly includes two kinds: serial technology and parallel technology. However, as the chip area decreases gradually, in parallel interconnection technology, it is more difficult to realize physical insulation between interconnection lines, clock deviation and signal crosstalk are becoming more and more serious. In addition, this technology needs to occupy a large number of pins on the chip. It increases the difficulty and cost of packaging and reduces the reliability. Therefore, an efficient and reliable protocol of fully interconnected serial interconnect interface is very important to the design of multi-chip architecture. In order to meet the requirement of real-time and high bandwidth of inter-chip interconnection interface in application field, this paper investigates the existing interconnection protocols, and proposes a fully interconnected serial interface protocol SLink. based on packet, with low delay, high bandwidth and high expansibility. The protocol consists of three parts: transaction layer, data link layer and physical layer. The protocol "packet" format is simple, LVDS technology is selected as the physical layer of data transmission basis, support configurable CRC verification and hardware detection retransmission mechanism. Based on the definition of SLink protocol, an implementation scheme is proposed, and the simulation evaluation data and the verification results of FPGA are given. The experimental results show that compared with PCI-Express 2.0 interface, the average transmission delay of SLink interface is reduced by 61.0, the effective bandwidth is increased by 55.6, and the area occupied by the controller is reduced by about 97.5.
【學(xué)位授予單位】：哈爾濱理工大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN405.97

【參考文獻(xiàn)】

相關(guān)期刊論文 前9條

1 胡冰;;PCI-E 3.0簡(jiǎn)介及信號(hào)和協(xié)議測(cè)試方法[J];中國(guó)集成電路;2016年12期

2 臧大偉;曹政;孫凝暉;;高性能計(jì)算的發(fā)展[J];科技導(dǎo)報(bào);2016年14期

3 胡曙凡;田澤;邵剛;;一種SerDes的高效集成可測(cè)試性設(shè)計(jì)[J];計(jì)算機(jī)技術(shù)與發(fā)展;2015年04期

4 鄧軍勇;李濤;蔣林;韓俊剛;杜慧敏;沈緒榜;黃光新;常立博;山蕊;黃虎才;馬棟;;MIGPU-9多核交互式圖形處理器的設(shè)計(jì)[J];計(jì)算機(jī)輔助設(shè)計(jì)與圖形學(xué)學(xué)報(bào);2014年09期

5 朱英;陳誠(chéng);許曉紅;李彥哲;;一款多核處理器FPGA驗(yàn)證平臺(tái)的設(shè)計(jì)與實(shí)現(xiàn)[J];計(jì)算機(jī)研究與發(fā)展;2014年06期

6 郭陽(yáng);李思昆;屈婉霞;;片上多核處理器驗(yàn)證:挑戰(zhàn)、現(xiàn)狀與展望[J];計(jì)算機(jī)輔助設(shè)計(jì)與圖形學(xué)學(xué)報(bào);2012年12期

7 梁小虎;王樂;張亞棣;;高速串行總線RapidIO與PCI Express協(xié)議分析比較[J];航空計(jì)算技術(shù);2010年03期

8 馬春江;牛文生;孫靖國(guó);;幾種串行總線互連技術(shù)分析[J];航空計(jì)算技術(shù);2007年05期

9 崔維嘉,樊少杰;新一代的總線結(jié)構(gòu)──RapidIO[J];通信技術(shù);2001年04期

相關(guān)碩士學(xué)位論文 前3條

1 王偉濤;8b/10b架構(gòu)SerDes芯片的設(shè)計(jì)與實(shí)現(xiàn)[D];電子科技大學(xué);2016年

2 王張萌;高速SERDES接口的關(guān)鍵電路設(shè)計(jì)[D];合肥工業(yè)大學(xué);2015年

3 陳超文;面向光纖通道的SerDes電路IP化技術(shù)研究[D];電子科技大學(xué);2014年

，

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