一種高效片間互聯(lián)接口協(xié)議的設(shè)計與實現(xiàn)
發(fā)布時間：2019-01-05 19:22
【摘要】：隨著半導(dǎo)體工藝的日趨成熟,超大規(guī)模集成電路迅猛發(fā)展。但傳統(tǒng)的單核處理器性能,與當(dāng)前亟待研究的計算密集型應(yīng)用需求,如核能開發(fā)、宇宙空間探索,以及炙手可熱的人工智能,仍存在不可逾越的鴻溝。因此,計算機體系結(jié)構(gòu)逐漸由單核向多核、眾核、多片發(fā)展。以Intel為代表的同構(gòu)多核、多片系統(tǒng)與以NVIDIA為代表的異構(gòu)多核、多片系統(tǒng),逐漸成為芯片設(shè)計的必然趨勢。在此背景下,如何準(zhǔn)確、高效地傳輸數(shù)據(jù),成為多核、多片系統(tǒng)中至關(guān)重要的技術(shù)重心與設(shè)計難點。片間互聯(lián)接口協(xié)議主要有兩種:支持路由功能的胖樹結(jié)構(gòu)協(xié)議,與不支持路由功能的全互聯(lián)結(jié)構(gòu)協(xié)議。當(dāng)計算處理器核數(shù)小于8時,由于胖樹結(jié)構(gòu)協(xié)議控制模塊設(shè)計復(fù)雜,多核之間需要交換機進行數(shù)據(jù)轉(zhuǎn)發(fā),所以互聯(lián)結(jié)構(gòu)占用的面積與功耗較大。片間互聯(lián)的實現(xiàn)技術(shù)主要包含兩種:串行技術(shù)和并行技術(shù)。但隨著芯片面積逐漸減小,并行互聯(lián)技術(shù)中,互聯(lián)線間實現(xiàn)物理絕緣難度加大,時鐘偏差與信號串?dāng)_也日趨嚴重,此外,該技術(shù)需要占用芯片大量的引腳數(shù),增大了封裝難度與成本,降低了可靠性。因此,一種高效、可靠的全互聯(lián)串行互聯(lián)接口協(xié)議對于多片架構(gòu)設(shè)計具有十分重要的意義。針對應(yīng)用領(lǐng)域?qū)ζg互聯(lián)接口實時性和高帶寬的需求,本文深入調(diào)研現(xiàn)有的互聯(lián)協(xié)議,提出一種基于“包”,具備低延遲、高帶寬以及高擴展性的全互聯(lián)串行互聯(lián)接口協(xié)議SLink。該協(xié)議由事務(wù)層、數(shù)據(jù)鏈路層和物理層三個部分組成。協(xié)議“包”格式簡潔,選擇LVDS技術(shù)作為物理層的數(shù)據(jù)傳輸基礎(chǔ),支持可配置的CRC校驗和硬件檢測重傳機制�；赟Link協(xié)議定義,提出一種實現(xiàn)方案,給出仿真評估數(shù)據(jù)及FPGA的驗證結(jié)果。實驗結(jié)果說明,相比PCI-Express 2.0接口,SLink接口傳輸延時平均減少61.0%,有效帶寬平均增加55.6%,控制器所占面積減小約97.5%。
[Abstract]:With the development of semiconductor technology, VLSI is developing rapidly. However, there is still an insurmountable gap between the performance of traditional single-core processors and the needs of computational intensive applications, such as nuclear energy development, space exploration, and the hot artificial intelligence. Therefore, the computer architecture is gradually developing from single core to multi-core, multi-core and multi-chip. Isomorphic multicore, multi-chip system represented by Intel and heterogeneous multi-core and multi-chip system represented by NVIDIA are becoming the inevitable trend of chip design. Under this background, how to transmit data accurately and efficiently becomes the most important technical center of gravity and design difficulty in multi-core and multi-chip system. There are two kinds of inter-chip interfacing protocols: fat tree protocol which supports routing function and full interconnection protocol which does not support routing function. When the number of processor cores is less than 8, due to the complexity of the design of the protocol control module of the fat-tree structure and the need for the switch to transmit the data between the multi-cores, the area and power consumption of the interconnected architecture are large. The realization technology of interchip interconnection mainly includes two kinds: serial technology and parallel technology. However, as the chip area decreases gradually, in parallel interconnection technology, it is more difficult to realize physical insulation between interconnection lines, clock deviation and signal crosstalk are becoming more and more serious. In addition, this technology needs to occupy a large number of pins on the chip. It increases the difficulty and cost of packaging and reduces the reliability. Therefore, an efficient and reliable protocol of fully interconnected serial interconnect interface is very important to the design of multi-chip architecture. In order to meet the requirement of real-time and high bandwidth of inter-chip interconnection interface in application field, this paper investigates the existing interconnection protocols, and proposes a fully interconnected serial interface protocol SLink. based on packet, with low delay, high bandwidth and high expansibility. The protocol consists of three parts: transaction layer, data link layer and physical layer. The protocol "packet" format is simple, LVDS technology is selected as the physical layer of data transmission basis, support configurable CRC verification and hardware detection retransmission mechanism. Based on the definition of SLink protocol, an implementation scheme is proposed, and the simulation evaluation data and the verification results of FPGA are given. The experimental results show that compared with PCI-Express 2.0 interface, the average transmission delay of SLink interface is reduced by 61.0, the effective bandwidth is increased by 55.6, and the area occupied by the controller is reduced by about 97.5.
【學(xué)位授予單位】：哈爾濱理工大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TN405.97
本文編號：2402198
[Abstract]:With the development of semiconductor technology, VLSI is developing rapidly. However, there is still an insurmountable gap between the performance of traditional single-core processors and the needs of computational intensive applications, such as nuclear energy development, space exploration, and the hot artificial intelligence. Therefore, the computer architecture is gradually developing from single core to multi-core, multi-core and multi-chip. Isomorphic multicore, multi-chip system represented by Intel and heterogeneous multi-core and multi-chip system represented by NVIDIA are becoming the inevitable trend of chip design. Under this background, how to transmit data accurately and efficiently becomes the most important technical center of gravity and design difficulty in multi-core and multi-chip system. There are two kinds of inter-chip interfacing protocols: fat tree protocol which supports routing function and full interconnection protocol which does not support routing function. When the number of processor cores is less than 8, due to the complexity of the design of the protocol control module of the fat-tree structure and the need for the switch to transmit the data between the multi-cores, the area and power consumption of the interconnected architecture are large. The realization technology of interchip interconnection mainly includes two kinds: serial technology and parallel technology. However, as the chip area decreases gradually, in parallel interconnection technology, it is more difficult to realize physical insulation between interconnection lines, clock deviation and signal crosstalk are becoming more and more serious. In addition, this technology needs to occupy a large number of pins on the chip. It increases the difficulty and cost of packaging and reduces the reliability. Therefore, an efficient and reliable protocol of fully interconnected serial interconnect interface is very important to the design of multi-chip architecture. In order to meet the requirement of real-time and high bandwidth of inter-chip interconnection interface in application field, this paper investigates the existing interconnection protocols, and proposes a fully interconnected serial interface protocol SLink. based on packet, with low delay, high bandwidth and high expansibility. The protocol consists of three parts: transaction layer, data link layer and physical layer. The protocol "packet" format is simple, LVDS technology is selected as the physical layer of data transmission basis, support configurable CRC verification and hardware detection retransmission mechanism. Based on the definition of SLink protocol, an implementation scheme is proposed, and the simulation evaluation data and the verification results of FPGA are given. The experimental results show that compared with PCI-Express 2.0 interface, the average transmission delay of SLink interface is reduced by 61.0, the effective bandwidth is increased by 55.6, and the area occupied by the controller is reduced by about 97.5.
【學(xué)位授予單位】：哈爾濱理工大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TN405.97
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