650V功率VDMOS結(jié)終端擴(kuò)展優(yōu)化設(shè)計(jì)
發(fā)布時(shí)間：2018-12-25 11:07
【摘要】：高壓VDMOS器件需要借助終端結(jié)構(gòu)來(lái)緩解結(jié)彎曲引起的曲率效應(yīng)。在VDMOS器件設(shè)計(jì)中,高擊穿電壓、短終端長(zhǎng)度、低漏電流和低表面電場(chǎng)峰值等性能參數(shù)的終端結(jié)構(gòu)對(duì)芯片的穩(wěn)定性和可靠性至關(guān)重要。聯(lián)合傳統(tǒng)的場(chǎng)板、場(chǎng)限環(huán)、結(jié)終端擴(kuò)展(JTE)等終端技術(shù)形成的復(fù)合終端結(jié)構(gòu)在學(xué)術(shù)界獲得廣泛研究。本文對(duì)650V VDMOS器件的多場(chǎng)限環(huán)(MFLR)、復(fù)合場(chǎng)板多場(chǎng)限環(huán)(FP-MFLR)、單區(qū)JTE和復(fù)合場(chǎng)板JTE(FP-JTE)四種終端結(jié)構(gòu)進(jìn)行優(yōu)化設(shè)計(jì)。通過(guò)分析PN結(jié)耐壓機(jī)理,采用碰撞電離率Lackner模型對(duì)650V VDMOS元胞結(jié)構(gòu)進(jìn)行仿真設(shè)計(jì)。并對(duì)其靜態(tài)參數(shù)進(jìn)行測(cè)試,擊穿電壓達(dá)到773.3V,導(dǎo)通電阻為6.73Ω,閾值電壓為2.66V,滿足了設(shè)計(jì)要求。此結(jié)構(gòu)為穿通型設(shè)計(jì),最大電場(chǎng)為2.55×10~5V/cm。在確定元胞結(jié)構(gòu)外延參數(shù)的基礎(chǔ)上,不改變工藝條件對(duì)單場(chǎng)限環(huán)、多場(chǎng)限環(huán)、金屬與多晶硅復(fù)合場(chǎng)板及單區(qū)JTE結(jié)構(gòu)進(jìn)行優(yōu)化。研究發(fā)現(xiàn),主結(jié)與場(chǎng)限環(huán)同時(shí)擊穿時(shí),擊穿點(diǎn)并不在同一水平線上,而是由內(nèi)向外逐漸靠近硅表面;最外環(huán)為非穿通型擊穿,其余各環(huán)為穿通型擊穿,各環(huán)結(jié)表面電場(chǎng)峰值從主結(jié)處由內(nèi)向外逐漸增大,主結(jié)處表面電場(chǎng)峰值略低于場(chǎng)限環(huán)處;金屬場(chǎng)板完全籠蓋住多晶硅,適當(dāng)?shù)亩嗑Ч韬徒饘賵?chǎng)板長(zhǎng)度使表面電場(chǎng)呈現(xiàn)三個(gè)峰值,多晶硅場(chǎng)板拉低主結(jié)與金屬場(chǎng)板兩處的表面電場(chǎng)峰值;密封保護(hù)環(huán)或者溝道截止環(huán)放置在耗盡層邊界外以避免對(duì)終端結(jié)構(gòu)的耐壓造成影響�；诖�,設(shè)計(jì)的6FLRs終端結(jié)構(gòu)耐壓達(dá)到679V,在183.8μm的終端長(zhǎng)度下,將表面電場(chǎng)峰值降低至2.34×10~5V/cm;將FP-MFLR結(jié)構(gòu)的終端長(zhǎng)度縮小至171.8μm,其耐壓達(dá)到700.0V,表面電場(chǎng)低至2.11×10~5V/cm;單區(qū)JTE結(jié)構(gòu)的耐壓為713.4V,終端長(zhǎng)度進(jìn)一步縮小至141.8μm,表面電場(chǎng)峰值在四種結(jié)構(gòu)中最小,值為1.9×10~5V/cm;FP-JTE結(jié)構(gòu)的擊穿電壓達(dá)到最大,值為757.7V,耐壓效率98%,幾乎接近元胞區(qū)結(jié)構(gòu)的擊穿電壓,具有最小的終端長(zhǎng)度139.2μm,表面電場(chǎng)峰值為2.28×1 05V/cm。除此之外,四種終端結(jié)構(gòu)均相容于傳統(tǒng)工藝,操作方便易實(shí)現(xiàn)。同時(shí),FP-MFLR與FP-JTE結(jié)構(gòu)受界面電荷影響小,穩(wěn)定性和可靠性相對(duì)較高。
[Abstract]:High voltage VDMOS devices need terminal structure to mitigate curvature effect caused by junction bending. In the design of VDMOS devices, the terminal structure with high breakdown voltage, short terminal length, low leakage current and low surface electric field peak value is very important to the stability and reliability of the chip. The structure of composite terminal formed by combining traditional terminal technologies such as field plate, field limiting ring and junction terminal extension (JTE) has been widely studied in academia. In this paper, four kinds of terminal structures of multifield limiting loop (FP-MFLR), single zone JTE and composite field plate JTE (FP-JTE) for 650V VDMOS devices are optimized. By analyzing the voltage resistance mechanism of PN junction and using the Lackner model of collision ionization rate, the cell structure of 650 V VDMOS was simulated and designed. The static parameters are tested, the breakdown voltage is 773.3 V, the on-resistance is 6.73 惟, and the threshold voltage is 2.66 V, which meets the design requirements. The maximum electric field is 2.55 脳 10 ~ (5) V / cm ~ (-1). On the basis of determining the cell structure epitaxial parameters, single field limiting ring, multiple field limiting ring, metal and polysilicon composite field plate and single zone JTE structure are optimized without changing the process conditions. It is found that when the main junction and the field limiting ring break down simultaneously, the breakdown point is not on the same horizontal line, but is gradually approaching the silicon surface from the inside out. The outmost ring is non-perforated breakdown, the other rings are perforated breakdown, the peak value of surface electric field increases from the main junction to the outside, and the peak value of the surface electric field at the main junction is slightly lower than that at the field limiting ring. The metal field plate completely covers the polycrystalline silicon, the proper length of the polycrystalline silicon and metal field plate makes the surface electric field show three peaks, and the polysilicon field plate lowers the surface electric field peak at the main junction and the metal field plate. The seal protection ring or the channel cutoff ring is placed outside the depletion layer boundary to avoid the pressure resistance of the terminal structure. Based on this, the designed 6FLRs terminal structure can withstand voltage up to 679V, and the peak value of surface electric field is reduced to 2.34 脳 10 ~ (5) V / cm at a terminal length of 183.8 渭 m. The terminal length of FP-MFLR structure is reduced to 171.8 渭 m, the voltage resistance is 700.0V, and the surface electric field is as low as 2.11 脳 10 ~ (5) V / cm. The voltage resistance of single-zone JTE structure is 713.4V, the terminal length is further reduced to 141.8 渭 m, and the peak value of surface electric field is the smallest among the four structures, with a value of 1.9 脳 10 ~ (5) V / cm. The breakdown voltage of FP-JTE structure reaches the maximum value (757.7V). The breakdown voltage of the FP-JTE structure is almost close to that of the cellular structure. It has the smallest terminal length of 139.2 渭 m and the peak surface electric field of 2.28 脳 10 5 V / cm ~ (-1). In addition, the four terminal structures are compatible with the traditional technology, easy to operate. At the same time, the structure of FP-MFLR and FP-JTE is less affected by interfacial charge, and its stability and reliability are relatively high.
【學(xué)位授予單位】：西南交通大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN386
本文編號(hào)：2391074
[Abstract]:High voltage VDMOS devices need terminal structure to mitigate curvature effect caused by junction bending. In the design of VDMOS devices, the terminal structure with high breakdown voltage, short terminal length, low leakage current and low surface electric field peak value is very important to the stability and reliability of the chip. The structure of composite terminal formed by combining traditional terminal technologies such as field plate, field limiting ring and junction terminal extension (JTE) has been widely studied in academia. In this paper, four kinds of terminal structures of multifield limiting loop (FP-MFLR), single zone JTE and composite field plate JTE (FP-JTE) for 650V VDMOS devices are optimized. By analyzing the voltage resistance mechanism of PN junction and using the Lackner model of collision ionization rate, the cell structure of 650 V VDMOS was simulated and designed. The static parameters are tested, the breakdown voltage is 773.3 V, the on-resistance is 6.73 惟, and the threshold voltage is 2.66 V, which meets the design requirements. The maximum electric field is 2.55 脳 10 ~ (5) V / cm ~ (-1). On the basis of determining the cell structure epitaxial parameters, single field limiting ring, multiple field limiting ring, metal and polysilicon composite field plate and single zone JTE structure are optimized without changing the process conditions. It is found that when the main junction and the field limiting ring break down simultaneously, the breakdown point is not on the same horizontal line, but is gradually approaching the silicon surface from the inside out. The outmost ring is non-perforated breakdown, the other rings are perforated breakdown, the peak value of surface electric field increases from the main junction to the outside, and the peak value of the surface electric field at the main junction is slightly lower than that at the field limiting ring. The metal field plate completely covers the polycrystalline silicon, the proper length of the polycrystalline silicon and metal field plate makes the surface electric field show three peaks, and the polysilicon field plate lowers the surface electric field peak at the main junction and the metal field plate. The seal protection ring or the channel cutoff ring is placed outside the depletion layer boundary to avoid the pressure resistance of the terminal structure. Based on this, the designed 6FLRs terminal structure can withstand voltage up to 679V, and the peak value of surface electric field is reduced to 2.34 脳 10 ~ (5) V / cm at a terminal length of 183.8 渭 m. The terminal length of FP-MFLR structure is reduced to 171.8 渭 m, the voltage resistance is 700.0V, and the surface electric field is as low as 2.11 脳 10 ~ (5) V / cm. The voltage resistance of single-zone JTE structure is 713.4V, the terminal length is further reduced to 141.8 渭 m, and the peak value of surface electric field is the smallest among the four structures, with a value of 1.9 脳 10 ~ (5) V / cm. The breakdown voltage of FP-JTE structure reaches the maximum value (757.7V). The breakdown voltage of the FP-JTE structure is almost close to that of the cellular structure. It has the smallest terminal length of 139.2 渭 m and the peak surface electric field of 2.28 脳 10 5 V / cm ~ (-1). In addition, the four terminal structures are compatible with the traditional technology, easy to operate. At the same time, the structure of FP-MFLR and FP-JTE is less affected by interfacial charge, and its stability and reliability are relatively high.
【學(xué)位授予單位】：西南交通大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN386
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