應(yīng)用于音頻設(shè)備的14bit∑-ΔADC的研究與設(shè)計(jì)
發(fā)布時(shí)間：2018-12-11 17:49
【摘要】：Sigma-delta模數(shù)轉(zhuǎn)化器(ADC)采用過采樣技術(shù)、噪聲整形技術(shù)和數(shù)字濾波技術(shù),完成對(duì)模擬信號(hào)的高精度轉(zhuǎn)換。本文針對(duì)AUDIO CODEC IP核項(xiàng)目的實(shí)際需求,設(shè)計(jì)了一款應(yīng)用于音頻設(shè)備的14bitSigma-delta ADC,包括sigma-delta模擬調(diào)制器部分和數(shù)字濾波器部分。Sigma-delta ADC的調(diào)制器部分,采用過采樣率(OSR)為256倍的2階1bit CIFB結(jié)構(gòu)。首先通過行為級(jí)綜合得到Sigma-delta調(diào)制器的噪聲傳輸函數(shù),然后運(yùn)用包含了電路級(jí)噪聲和非理想因素影響的simulink模型進(jìn)行行為級(jí)仿真,最終電路實(shí)現(xiàn)。Sigma-delta ADC的數(shù)字濾波器部分,采用三級(jí)有限脈沖響應(yīng)(FIR)抽取濾波器級(jí)聯(lián)結(jié)構(gòu),順次為梳狀濾波器(CIC)/半袋濾波器(HBF1)/半帶濾波器(HBF2)。通過行為級(jí)simulink建模仿真并最終交付數(shù)字前端完成Verilog HDL編寫。在華力55nm CMOS工藝下,Sigma-delta調(diào)制器部分采用的是開關(guān)電容積分電路來實(shí)現(xiàn)的。在調(diào)制器電路設(shè)計(jì)上,各級(jí)積分器采用特殊的開關(guān)控制以減小電容面積;設(shè)計(jì)了兩級(jí)運(yùn)算放大器、兩相不交疊時(shí)鐘、動(dòng)態(tài)鎖存比較器;帶隙基準(zhǔn)源電路為帶高階補(bǔ)償?shù)耐負(fù)浣Y(jié)構(gòu),溫度系數(shù)(TC)可達(dá)到4.87ppm/℃。對(duì)整個(gè)調(diào)制器部分完成了測試,其結(jié)果可以達(dá)到SNDR=84.1dB(13.67 bits),滿足設(shè)計(jì)需求。
[Abstract]:Sigma-delta analog-to-digital converter (ADC) uses over-sampling technology, noise shaping technology and digital filtering technology to complete the high-precision conversion of analog signals. According to the actual requirement of AUDIO CODEC IP nuclear project, this paper designs a 14bitSigma-delta ADC, for audio equipment, which includes sigma-delta analog modulator part and digital filter part. Sigma-delta ADC modulator part. The second order 1bit CIFB structure with an oversampling rate of 256-fold (OSR) is adopted. First, the noise transfer function of Sigma-delta modulator is obtained by synthesizing the behavior level, then the behavioral level simulation is carried out by using the simulink model which includes the circuit level noise and the influence of non-ideal factors. Finally, the digital filter part of Sigma-delta ADC is realized by the circuit. A cascade structure of three-stage finite pulse response (FIR) decimation filter is adopted. The sequence is comb filter (CIC) / half-bag filter (HBF1) / half-band filter (HBF2). Through behavioral simulink modeling and simulation and finally delivered to the digital front-end to complete the Verilog HDL programming. In the 55nm CMOS process, the Sigma-delta modulator is implemented by the switched capacitor integral circuit. In the circuit design of modulator, the integrator adopts special switch control to reduce the capacitance area, a two-stage operational amplifier, two phase non-overlapping clock, dynamic latch comparator is designed. The bandgap reference circuit is a topology with high order compensation, and the temperature coefficient (TC) can reach 4.87ppm/ 鈩，
本文編號(hào)：2372968
[Abstract]:Sigma-delta analog-to-digital converter (ADC) uses over-sampling technology, noise shaping technology and digital filtering technology to complete the high-precision conversion of analog signals. According to the actual requirement of AUDIO CODEC IP nuclear project, this paper designs a 14bitSigma-delta ADC, for audio equipment, which includes sigma-delta analog modulator part and digital filter part. Sigma-delta ADC modulator part. The second order 1bit CIFB structure with an oversampling rate of 256-fold (OSR) is adopted. First, the noise transfer function of Sigma-delta modulator is obtained by synthesizing the behavior level, then the behavioral level simulation is carried out by using the simulink model which includes the circuit level noise and the influence of non-ideal factors. Finally, the digital filter part of Sigma-delta ADC is realized by the circuit. A cascade structure of three-stage finite pulse response (FIR) decimation filter is adopted. The sequence is comb filter (CIC) / half-bag filter (HBF1) / half-band filter (HBF2). Through behavioral simulink modeling and simulation and finally delivered to the digital front-end to complete the Verilog HDL programming. In the 55nm CMOS process, the Sigma-delta modulator is implemented by the switched capacitor integral circuit. In the circuit design of modulator, the integrator adopts special switch control to reduce the capacitance area, a two-stage operational amplifier, two phase non-overlapping clock, dynamic latch comparator is designed. The bandgap reference circuit is a topology with high order compensation, and the temperature coefficient (TC) can reach 4.87ppm/ 鈩，
本文編號(hào)：2372968
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