【摘要】：隨著集成電路的高速發(fā)展,對(duì)芯片時(shí)鐘頻率精確度的要求也越來(lái)越高。頻率源的準(zhǔn)確性可以決定一個(gè)時(shí)序電路設(shè)計(jì)的質(zhì)量。尤其是在如今高速集成的數(shù)字電路中,一個(gè)細(xì)小的時(shí)鐘誤差就可能導(dǎo)致整體周期的錯(cuò)亂,使得數(shù)字電路的時(shí)序紊亂。因此,振蕩器作為集成電路頻率源的代表成為了人們關(guān)注的研究課題。本論首先文介紹了目前較為流行的三種在集成電路中應(yīng)用的振蕩器,它們分別是晶體振蕩器、環(huán)形振蕩器以及張弛振蕩器。隨之逐一地分析了它們的結(jié)構(gòu)特點(diǎn)以及工作方原理。本文基于TSMC90nm工藝設(shè)計(jì)了一款頻率可修調(diào)的張弛振蕩器,并且還設(shè)計(jì)了一款低功耗的線性穩(wěn)壓器來(lái)驅(qū)動(dòng)振蕩器。文中詳細(xì)地闡述了線性穩(wěn)壓器的設(shè)計(jì)原理,并結(jié)合其自身的特點(diǎn)提出了一種低功耗并且十分節(jié)省面積的設(shè)計(jì)方案。隨后對(duì)其進(jìn)行仿真驗(yàn)證,得到了一個(gè)可靠的輸出電壓為1.2V的線性穩(wěn)壓器。仿真結(jié)果表明線性穩(wěn)壓器的負(fù)載調(diào)整率為3.64%以及其電源抑制比為-63.4dB。隨后,根據(jù)設(shè)計(jì)要求完成了對(duì)振蕩器電路的總體結(jié)構(gòu)設(shè)計(jì)和子模塊的電路設(shè)計(jì)。并詳細(xì)地講述了如何通過(guò)修調(diào)控制端口的連接方式來(lái)得到所需的輸出振蕩頻率。通過(guò)調(diào)節(jié)控制端口課時(shí)輸出頻率覆蓋范圍達(dá)到默認(rèn)值的284%至61.5%內(nèi),并且仿真數(shù)據(jù)驗(yàn)證了在如此大的范圍內(nèi)一定可以找到最初設(shè)定的頻率為48MHz的振蕩器。而后為了確保輸出時(shí)鐘的可靠性,還專門地討論了其相位噪聲,仿真實(shí)驗(yàn)結(jié)果測(cè)得相位噪聲可達(dá)-101.128dBc/Hz @1MHz,以及-121.806dBc/Hz @10MHz。最后,本文繪制出了線性穩(wěn)壓器與振蕩器的版圖,并分別對(duì)其進(jìn)行后仿驗(yàn)證,仿真結(jié)果均滿足設(shè)計(jì)要求。
[Abstract]:With the rapid development of integrated circuits, the precision of clock frequency is becoming more and more important. The accuracy of the frequency source can determine the quality of a sequential circuit design. Especially in today's high-speed integrated digital circuits, a small clock error may lead to the disorder of the whole cycle and the timing disorder of the digital circuits. Therefore, oscillator as the representative of integrated circuit frequency source has become a research topic. This paper first introduces three kinds of oscillators used in integrated circuits, which are crystal oscillator, ring oscillator and Zhang Chi oscillator. Then the structural characteristics and the working principle are analyzed one by one. In this paper, a frequency adjustable Zhang Chi oscillator is designed based on TSMC90nm process, and a low power linear voltage regulator is designed to drive the oscillator. In this paper, the design principle of linear voltage regulator is described in detail, and a design scheme of low power consumption and very low area saving is put forward according to its own characteristics. A reliable linear voltage regulator with 1.2 V output voltage is obtained by simulation. The simulation results show that the load adjustment rate of the linear regulator is 3.64% and the power rejection ratio is -63.4 dB. Then, the overall structure of the oscillator circuit and the circuit design of the sub-module are completed according to the design requirements. How to obtain the output oscillation frequency by adjusting the connection mode of the control port is described in detail. By adjusting the output frequency coverage range of the control port within 284% to 61.5% of the default value, the simulation data verify that the oscillator with the initial frequency of 48MHz can be found in such a wide range. Then, in order to ensure the reliability of the output clock, the phase noise of the clock is also discussed. The simulation results show that the phase noise can reach-101.128dBc/Hz @ 1MHz, and-121.806dBc/Hz @ 10MHz. Finally, the layout of the linear voltage regulator and the oscillator is drawn, and the simulation results meet the design requirements.
【學(xué)位授予單位】：北方工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN752

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本文編號(hào)：2364998