【摘要】：功耗是電路設(shè)計(jì)的關(guān)鍵性問(wèn)題之一,低功耗下的穩(wěn)定性問(wèn)題逐漸成為電路設(shè)計(jì)的熱點(diǎn)和挑戰(zhàn),基于馬爾科夫隨機(jī)場(chǎng)(MRF)的低功耗設(shè)計(jì)從能量的角度出發(fā)有效地解決了電路的容錯(cuò)問(wèn)題,但是其單邏輯的單元結(jié)構(gòu)面積和復(fù)雜度制約了該技術(shù)在大規(guī)模集成電路的應(yīng)用。該文提出了一種基于部分簇能量的MRF電路設(shè)計(jì)方法(PMRF),并結(jié)合互補(bǔ)邏輯的特點(diǎn)來(lái)實(shí)現(xiàn)多邏輯結(jié)構(gòu),面積共享的同時(shí)一方面補(bǔ)償由于部分簇能量帶來(lái)的性能損失,一方面化簡(jiǎn)馬氏隨機(jī)場(chǎng)電路設(shè)計(jì)在較大規(guī)模電路設(shè)計(jì)中的面積和復(fù)雜度瓶頸問(wèn)題。對(duì)比傳統(tǒng)MRF電路設(shè)計(jì),該文用PMRF方法設(shè)計(jì)了超前進(jìn)位加法器結(jié)構(gòu),在低功耗仿真中具有20%的性能提升,并在65 nm TSMC版圖實(shí)現(xiàn)后取得29%的面積節(jié)約和86%的功耗節(jié)約。
[Abstract]:Power consumption is one of the key problems in circuit design. The low power design based on Markov random field (MRF) effectively solves the fault tolerance problem of circuits from the point of view of energy. However, the area and complexity of single logic cell structure restrict the application of this technology in large scale integrated circuits (LSI). In this paper, a design method of MRF circuit based on partial cluster energy (PMRF),) is proposed, which combines the characteristics of complementary logic to realize multi-logic structure. On the one hand, area sharing compensates for the loss of performance caused by partial cluster energy. On the one hand, the area and complexity bottleneck of Mahalanobis random field circuit design in large scale circuit design. Compared with traditional MRF circuit design, this paper uses PMRF method to design ahead carry adder structure, which has 20% performance improvement in low power simulation, and achieves 29% area saving and 86% power saving after 65 nm TSMC layout implementation.
【作者單位】： 電子科技大學(xué)通信抗干擾國(guó)家級(jí)重點(diǎn)實(shí)驗(yàn)室;
【基金】：國(guó)家自然科學(xué)基金(61371104)
【分類號(hào)】：TN402
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本文編號(hào)：2349623