基于電荷平衡的超結(jié)LDMOS仿真和工藝設(shè)計(jì)
發(fā)布時(shí)間：2018-11-20 09:35
【摘要】：人們現(xiàn)在的生活與娛樂(lè)經(jīng)常伴隨著手機(jī)、電腦、平板等電子產(chǎn)品。在任何電子產(chǎn)品中,電源是必不可少的組成部分,而功率半導(dǎo)體器件是對(duì)電源電流和電壓處理的必要單元。功率半導(dǎo)體器件經(jīng)過(guò)六十多年的發(fā)展,已經(jīng)形成了一個(gè)龐大的家族。新的家族成員憑借其自身優(yōu)良的電學(xué)特性不斷侵蝕著原先成員的應(yīng)用市場(chǎng)。功率半導(dǎo)體器件中,MOS器件沒(méi)有自熱效應(yīng),不會(huì)發(fā)生二次擊穿,為電壓控制型器件,其驅(qū)動(dòng)電路簡(jiǎn)單。這些優(yōu)點(diǎn)使其得到了廣泛的應(yīng)用。在功率MOS器件設(shè)計(jì)中,擊穿電壓與比導(dǎo)通電阻的對(duì)立關(guān)系很嚴(yán)峻。為了解決這一矛盾,超結(jié)結(jié)構(gòu)提了出來(lái)。該結(jié)構(gòu)不僅有著電學(xué)特性優(yōu)良的特點(diǎn)同時(shí)還有著很好的技術(shù)轉(zhuǎn)移特性。這些優(yōu)點(diǎn)使其被稱為“功率器件發(fā)展史上的里程碑”。近幾年來(lái),超結(jié)結(jié)構(gòu)的應(yīng)用和優(yōu)化的研究十分熱門�？v向超結(jié)結(jié)構(gòu)的優(yōu)勢(shì)很大,擁有良好的電學(xué)特性,目前主要對(duì)其制作工藝進(jìn)行開發(fā)。橫向超結(jié)結(jié)構(gòu)雖然存在襯底輔助耗盡效應(yīng),影響了其應(yīng)用,但是縱向超結(jié)結(jié)構(gòu)的成功,使人們看到了橫向超結(jié)結(jié)構(gòu)的巨大潛力,從而出現(xiàn)了多種多樣對(duì)其優(yōu)化的結(jié)構(gòu)和技術(shù)。本文在前人工作的基礎(chǔ)上,從電荷平衡的角度消除襯底輔助耗盡效應(yīng),提出了兩種新型的器件結(jié)構(gòu),利用仿真軟件ISE TCAD 10.0對(duì)兩種器件結(jié)構(gòu)進(jìn)行設(shè)計(jì)優(yōu)化和電學(xué)特性的仿真分析。兩種新型的器件分別為DNU SJ-LDMOS(具有N柱分區(qū)非平衡SJ-LDMOS)和NBB SJ-LDMOS(具有N型埋層Buffer SJ-LDMOS)。通過(guò)仿真,在相同參數(shù)的條件下,對(duì)DNU SJ-LDMOS與平衡SJ-LDMOS進(jìn)行了電學(xué)特性對(duì)比。DNU SJ-LDMOS比SJ-LDMOS的比導(dǎo)通電阻降低14.08%,擊穿電壓提高38.74%。對(duì)DNU SJ-LDMOS的分區(qū)濃度,分區(qū)長(zhǎng)度,分區(qū)個(gè)數(shù)等影響器件電學(xué)特性的參數(shù)進(jìn)行優(yōu)化設(shè)計(jì),可以得到器件的比導(dǎo)通電阻為46.99mΩ?cm2,擊穿電壓為207.0V。同樣,在相同參數(shù)的條件下,對(duì)NBB SJ-LDMOS、傳統(tǒng)SJ-LDMOS和Buffer SJ-LDMOS進(jìn)行了電學(xué)特性對(duì)比。對(duì)比于傳統(tǒng)SJ-LDMOS,Buffer SJ-LDMOS和NBB SJ-LDMOS依次降低比導(dǎo)通電阻27.8%,38.1%,擊穿電壓分別提高11.7%、62.6%。對(duì)比于Buffer SJ-LDMOS,NBB SJ-LDMOS降低比導(dǎo)通電阻21.8%,擊穿電壓提高了45.5%。對(duì)NBB SJ-LDMOS的N埋層濃度,N埋層厚度,N埋層長(zhǎng)度等影響器件電學(xué)特性的參數(shù)進(jìn)行優(yōu)化設(shè)計(jì),可以得到器件的比導(dǎo)通電阻為82.38mΩ?cm2,擊穿電壓為322.8V。最后本文介紹了功率器件的BCD工藝以及傳統(tǒng)SJ-LDMOS的工藝流程,開發(fā)了DNU SJ-LDMOS和NBB SJ-LDMOS的工藝流程,同時(shí)設(shè)計(jì)了工藝中所用的版圖。
[Abstract]:People's life and entertainment are often accompanied by mobile phones, computers, tablets and other electronic products. In any electronic product, power supply is an essential component, and power semiconductor devices are necessary units for power supply current and voltage processing. After more than 60 years of development, power semiconductor devices have formed a large family. The new members of the family continue to erode the application market of the original members by virtue of their own excellent electrical properties. In the power semiconductor devices, the MOS device has no self-heating effect and no secondary breakdown. It is a voltage-controlled device and its driving circuit is simple. These advantages make it widely used. In the design of power MOS devices, the relationship between breakdown voltage and specific on-resistance is very severe. In order to solve this contradiction, the superjunction structure was proposed. The structure has not only excellent electrical properties but also good technology transfer characteristics. These advantages make it known as a milestone in the history of power device development. In recent years, the application and optimization of superjunction structures are very popular. The longitudinal superjunction structure has great advantages and good electrical properties. At present, its fabrication process is mainly developed. Although there exists substrate-assisted depletion effect in transverse superjunction structures, the success of longitudinal superjunction structures makes people see the great potential of transverse superjunction structures, thus various structures and techniques for their optimization have emerged. In this paper, based on the previous work, two novel device structures are proposed to eliminate the substrate-assisted depletion effect from the angle of charge balance. The simulation software ISE TCAD 10.0 is used to optimize the design of the two devices and to analyze the electrical characteristics. The two novel devices are DNU SJ-LDMOS (with N-column nonequilibrium SJ-LDMOS) and NBB SJ-LDMOS (with N-type buried Buffer SJ-LDMOS). Through simulation, the electrical characteristics of DNU SJ-LDMOS and balanced SJ-LDMOS are compared under the same parameters. The specific on-resistance of DNU SJ-LDMOS is 14.08 lower than that of SJ-LDMOS, and the breakdown voltage is increased 38.74. By optimizing the design of the parameters which affect the electrical properties of DNU SJ-LDMOS, such as the concentration, length and number of zones, the specific on-resistance of the device is 46.99m 惟? cm2, breakdown voltage is 207.0V. The electrical properties of NBB SJ-LDMOS, traditional SJ-LDMOS and Buffer SJ-LDMOS are also compared under the same parameters. Compared with the conventional SJ-LDMOS,Buffer SJ-LDMOS and NBB SJ-LDMOS, the specific on-resistance of 27.8% and 38.1% were decreased in turn, and the breakdown voltage was increased by 11.7% and 62.6%, respectively. Compared with Buffer SJ-LDMOS,NBB SJ-LDMOS, the breakdown voltage increased by 45.5%. The parameters affecting the electrical properties of NBB SJ-LDMOS, such as N buried layer concentration, N buried layer thickness and N buried layer length, are optimized. The specific on-resistance of the device is 82.38 m 惟? cm2, breakdown voltage is 322.8V. Finally, this paper introduces the BCD process of power device and the process flow of traditional SJ-LDMOS, develops the process flow of DNU SJ-LDMOS and NBB SJ-LDMOS, and designs the layout used in the process.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN386
本文編號(hào)：2344548
[Abstract]:People's life and entertainment are often accompanied by mobile phones, computers, tablets and other electronic products. In any electronic product, power supply is an essential component, and power semiconductor devices are necessary units for power supply current and voltage processing. After more than 60 years of development, power semiconductor devices have formed a large family. The new members of the family continue to erode the application market of the original members by virtue of their own excellent electrical properties. In the power semiconductor devices, the MOS device has no self-heating effect and no secondary breakdown. It is a voltage-controlled device and its driving circuit is simple. These advantages make it widely used. In the design of power MOS devices, the relationship between breakdown voltage and specific on-resistance is very severe. In order to solve this contradiction, the superjunction structure was proposed. The structure has not only excellent electrical properties but also good technology transfer characteristics. These advantages make it known as a milestone in the history of power device development. In recent years, the application and optimization of superjunction structures are very popular. The longitudinal superjunction structure has great advantages and good electrical properties. At present, its fabrication process is mainly developed. Although there exists substrate-assisted depletion effect in transverse superjunction structures, the success of longitudinal superjunction structures makes people see the great potential of transverse superjunction structures, thus various structures and techniques for their optimization have emerged. In this paper, based on the previous work, two novel device structures are proposed to eliminate the substrate-assisted depletion effect from the angle of charge balance. The simulation software ISE TCAD 10.0 is used to optimize the design of the two devices and to analyze the electrical characteristics. The two novel devices are DNU SJ-LDMOS (with N-column nonequilibrium SJ-LDMOS) and NBB SJ-LDMOS (with N-type buried Buffer SJ-LDMOS). Through simulation, the electrical characteristics of DNU SJ-LDMOS and balanced SJ-LDMOS are compared under the same parameters. The specific on-resistance of DNU SJ-LDMOS is 14.08 lower than that of SJ-LDMOS, and the breakdown voltage is increased 38.74. By optimizing the design of the parameters which affect the electrical properties of DNU SJ-LDMOS, such as the concentration, length and number of zones, the specific on-resistance of the device is 46.99m 惟? cm2, breakdown voltage is 207.0V. The electrical properties of NBB SJ-LDMOS, traditional SJ-LDMOS and Buffer SJ-LDMOS are also compared under the same parameters. Compared with the conventional SJ-LDMOS,Buffer SJ-LDMOS and NBB SJ-LDMOS, the specific on-resistance of 27.8% and 38.1% were decreased in turn, and the breakdown voltage was increased by 11.7% and 62.6%, respectively. Compared with Buffer SJ-LDMOS,NBB SJ-LDMOS, the breakdown voltage increased by 45.5%. The parameters affecting the electrical properties of NBB SJ-LDMOS, such as N buried layer concentration, N buried layer thickness and N buried layer length, are optimized. The specific on-resistance of the device is 82.38 m 惟? cm2, breakdown voltage is 322.8V. Finally, this paper introduces the BCD process of power device and the process flow of traditional SJ-LDMOS, develops the process flow of DNU SJ-LDMOS and NBB SJ-LDMOS, and designs the layout used in the process.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN386
【參考文獻(xiàn)】
相關(guān)期刊論文 前2條
1 黃示;郭宇鋒;姚佳飛;夏曉娟;徐躍;張瑛;;橫向超結(jié)器件襯底輔助耗盡效應(yīng)的研究與展望[J];微電子學(xué);2013年04期
2 陳星弼;;超結(jié)器件[J];電力電子技術(shù);2008年12期
，本文編號(hào)：2344548
本文鏈接：http://sikaile.net/kejilunwen/dianzigongchenglunwen/2344548.html
最近更新
教材專著
