【摘要】：逐次逼近模數(shù)轉(zhuǎn)換器(ADC)具有中等轉(zhuǎn)換速度和中等轉(zhuǎn)換精度,采用CMOS工藝實現(xiàn)可以保證較小的芯片面積和低功耗,而且便于實現(xiàn)多路轉(zhuǎn)換,在功耗、精度、速度和成本方面具有綜合優(yōu)勢,被廣泛應(yīng)用于無線通信、工業(yè)控制、醫(yī)療儀器以及微處理器輔助模數(shù)轉(zhuǎn)換接口等領(lǐng)域。本文設(shè)計了一個精度為10bit,速度為10Ms/s的低功耗逐次逼近ADC。電路采用差分輸入,同步時鐘,并具有省電模式。工作在完成ADC電路設(shè)計仿真的基礎(chǔ)上,完成了整個電路的物理版圖設(shè)計及后仿真。該逐次逼近ADC采用GSMC 0.18um混合信號CMOS工藝設(shè)計,芯片面積為0.8mm×0.8mm。版圖后防真結(jié)果顯示,在10Ms/s下,其SNDR為59.38dB,即ENOB為9.57位,
[Abstract]:The successive approximation analog-to-digital converter (ADC) has medium conversion speed and medium conversion precision. Using CMOS technology can guarantee small chip area and low power consumption, and it is easy to realize multiplexing, power consumption and precision. The advantages of speed and cost are widely used in wireless communication, industrial control, medical instruments and microprocessor aided A / D conversion interface and so on. In this paper, a low power successive approximation ADC. with an accuracy of 10 bits and a speed of 10Ms/s is designed. The circuit uses differential input, synchronous clock and power saving mode. On the basis of ADC circuit design and simulation, the physical layout design and post simulation of the whole circuit are completed. The successive approximation ADC is designed by GSMC 0.18um mixed signal CMOS process. The chip area is 0.8mm 脳 0.8mm. The result shows that under 10Ms/s, its SNDR is 59.38 dB, that is, ENOB is 9.57 bits.
【學(xué)位授予單位】：蘇州大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2016
【分類號】：TN792

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本文編號：2328734