基于FPGA的光時域反射儀信號采集系統(tǒng)設(shè)計
發(fā)布時間：2018-11-10 06:50
【摘要】：OTDR（Optical Time Domain Reflectometer，光時域反射儀）是一種光纖測量專用儀器，它根據(jù)瑞利散射測算出光纖延長度的損耗信息，根據(jù)菲涅爾反射定位光纖事件位置，，是光纖通信領(lǐng)域不可缺少的測量和維護設(shè)備。目前，OTDR除了要具備大動態(tài)范圍、小盲區(qū)、高分辨率等性能，還要具備較強的數(shù)據(jù)交換能力以及較快的數(shù)據(jù)處理能力。信號采集系統(tǒng)作為OTDR主要組成部分，承擔著OTDR返回光信號的采集、存儲、傳輸、處理的重要功能。隨著實際工程對OTDR的性能要求越來越高，OTDR對信號采集系統(tǒng)也提出了更高的要求。 本文在對數(shù)據(jù)采集技術(shù)以及OTDR原理的研究基礎(chǔ)上，結(jié)合OTDR的發(fā)展需要，以實現(xiàn)信號高速采集、數(shù)據(jù)高無縫速存儲和傳輸、改善信噪比為目標，提出一種基于FPGA的光時域反射儀信號采集系統(tǒng)。該系統(tǒng)以Altera公司的FPGA芯片EP4CE40F23C8N作為核心控制芯片，利用高性能低功耗模數(shù)轉(zhuǎn)換芯片AD9230進行快速數(shù)字化，考慮了采集系統(tǒng)數(shù)據(jù)存儲和數(shù)據(jù)傳輸高速和實時的需要，利用兩片SRAM存儲器ISSI61LV25616通過乒乓操作進行數(shù)據(jù)存儲，同時結(jié)合USB接口高速數(shù)據(jù)吞吐的優(yōu)勢，使用USB數(shù)據(jù)線實現(xiàn)與上位機的數(shù)據(jù)傳遞，最終實現(xiàn)光時域反射儀信號采集系統(tǒng)。 本系統(tǒng)由硬件與軟件共同組成。系統(tǒng)硬件設(shè)計包括FPGA核心電路模塊、信號接收與調(diào)理電路模塊、模數(shù)轉(zhuǎn)換電路模塊、數(shù)據(jù)存儲電路模塊、USB接口電路模塊、時鐘晶振與電源電路模塊，本文對各模塊的設(shè)計思路和電路進行了介紹。系統(tǒng)軟件設(shè)計包括下位機FPGA邏輯功能設(shè)計和上位機信號線性累加處理。其中，F(xiàn)PGA邏輯功能設(shè)計部分分為AD控制模塊、FIFO緩沖模塊、存儲控制模塊、USB接口控制模塊等，本文從狀態(tài)轉(zhuǎn)換、邏輯功能等方面對各個模塊進行了說明，并應(yīng)用Modelsim軟件對各個模塊進行了功能仿真。信號線性累加處理部分介紹了算法主要流程，應(yīng)用Matlab軟件設(shè)計了圖型顯示界面并實現(xiàn)了線性累加算法的仿真。
[Abstract]:OTDR (Optical Time Domain Reflectometer, optical time domain reflectometer (OTDR) is a special optical fiber measurement instrument, which calculates the loss information of fiber extension according to Rayleigh scattering, and locates the location of optical fiber event according to Fresnel reflection. Is an indispensable measurement and maintenance equipment in the field of optical fiber communication. At present, OTDR not only has large dynamic range, small blind area, high resolution and so on, but also has strong data exchange ability and fast data processing ability. As the main component of OTDR, the signal acquisition system is responsible for the important functions of OTDR signal acquisition, storage, transmission and processing. With the higher performance requirements of OTDR in practical engineering, OTDR also puts forward higher requirements for signal acquisition system. Based on the research of data acquisition technology and OTDR principle, combined with the development needs of OTDR, this paper aims to achieve high-speed signal acquisition, high-speed storage and transmission of data, and improve signal-to-noise ratio (SNR). A signal acquisition system for optical time domain reflectometer based on FPGA is proposed. In this system, the FPGA chip EP4CE40F23C8N of Altera Company is used as the core control chip, and the high performance and low power A / D conversion chip AD9230 is used for fast digitization. The requirement of high speed and real time data storage and data transmission in the acquisition system is considered. Two pieces of SRAM memory ISSI61LV25616 are used to store data through ping-pong operation. At the same time, combined with the advantage of high-speed data throughput of USB interface, the data transfer between PC and PC is realized by using USB data line. Finally, the signal acquisition system of optical time domain reflectometer is realized. The system is composed of hardware and software. The system hardware design includes FPGA core circuit module, signal receiving and conditioning circuit module, analog-to-digital conversion circuit module, data storage circuit module, USB interface circuit module, clock crystal oscillator and power supply circuit module. The design idea and circuit of each module are introduced in this paper. The software design of the system includes the logic function design of the lower computer FPGA and the linear accumulative processing of the upper computer signal. Among them, FPGA logic function design is divided into AD control module, FIFO buffer module, storage control module, USB interface control module, etc. The function of each module is simulated by Modelsim software. In the part of signal linear accumulation processing, the main flow of the algorithm is introduced. The graphic display interface is designed by using Matlab software and the simulation of linear accumulation algorithm is realized.
【學位授予單位】：太原理工大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TP274.2;TN791
本文編號：2321671
[Abstract]:OTDR (Optical Time Domain Reflectometer, optical time domain reflectometer (OTDR) is a special optical fiber measurement instrument, which calculates the loss information of fiber extension according to Rayleigh scattering, and locates the location of optical fiber event according to Fresnel reflection. Is an indispensable measurement and maintenance equipment in the field of optical fiber communication. At present, OTDR not only has large dynamic range, small blind area, high resolution and so on, but also has strong data exchange ability and fast data processing ability. As the main component of OTDR, the signal acquisition system is responsible for the important functions of OTDR signal acquisition, storage, transmission and processing. With the higher performance requirements of OTDR in practical engineering, OTDR also puts forward higher requirements for signal acquisition system. Based on the research of data acquisition technology and OTDR principle, combined with the development needs of OTDR, this paper aims to achieve high-speed signal acquisition, high-speed storage and transmission of data, and improve signal-to-noise ratio (SNR). A signal acquisition system for optical time domain reflectometer based on FPGA is proposed. In this system, the FPGA chip EP4CE40F23C8N of Altera Company is used as the core control chip, and the high performance and low power A / D conversion chip AD9230 is used for fast digitization. The requirement of high speed and real time data storage and data transmission in the acquisition system is considered. Two pieces of SRAM memory ISSI61LV25616 are used to store data through ping-pong operation. At the same time, combined with the advantage of high-speed data throughput of USB interface, the data transfer between PC and PC is realized by using USB data line. Finally, the signal acquisition system of optical time domain reflectometer is realized. The system is composed of hardware and software. The system hardware design includes FPGA core circuit module, signal receiving and conditioning circuit module, analog-to-digital conversion circuit module, data storage circuit module, USB interface circuit module, clock crystal oscillator and power supply circuit module. The design idea and circuit of each module are introduced in this paper. The software design of the system includes the logic function design of the lower computer FPGA and the linear accumulative processing of the upper computer signal. Among them, FPGA logic function design is divided into AD control module, FIFO buffer module, storage control module, USB interface control module, etc. The function of each module is simulated by Modelsim software. In the part of signal linear accumulation processing, the main flow of the algorithm is introduced. The graphic display interface is designed by using Matlab software and the simulation of linear accumulation algorithm is realized.
【學位授予單位】：太原理工大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TP274.2;TN791
【參考文獻】
相關(guān)期刊論文 前10條
1 劉恒;孟瑞麗;;非線性微機械諧振器的頻率跟蹤控制及數(shù)值仿真[J];傳感技術(shù)學報;2012年03期
2 何玲玲;張仲;葛立峰;;基于LabVIEW的微弱光電信號采集與處理系統(tǒng)的設(shè)計[J];電測與儀表;2010年06期
3 李芮;李曉;王志斌;王國梁;;基于SRAM乒乓操作的數(shù)據(jù)采集系統(tǒng)的設(shè)計[J];濟南大學學報(自然科學版);2015年02期
4 盧春暉;王英健;陳麗;;提升小波算法的FPGA硬件實現(xiàn)[J];微處理機;2010年02期
5 李偵;田夢君;趙菲菲;;基于DSP的無人飛行器飛行控制系統(tǒng)設(shè)計[J];微處理機;2010年04期
6 莫建文;歐陽繕;肖海林;孫希延;;陣列雙穩(wěn)隨機共振在微弱信號檢測中的應(yīng)用研究[J];信號處理;2011年05期
7 徐閩斌;李建新;楊天池;;微弱信號的相位檢測技術(shù)研究[J];信息工程大學學報;2010年01期
8 張雷;吳華夏;胡俊濤;呂國強;;一種基于FPGA的OLED顯示系統(tǒng)[J];液晶與顯示;2011年04期
9 李秀坤;李婷婷;馬濤;;微弱信號強干擾分離方法研究[J];振動與沖擊;2011年03期
10 樊養(yǎng)余;李利品;黨瑞榮;;基于隨機共振的任意大頻率微弱信號檢測方法研究[J];儀器儀表學報;2013年03期
本文編號：2321671
本文鏈接：http://sikaile.net/kejilunwen/dianzigongchenglunwen/2321671.html
最近更新
教材專著
