4GSPS任意波形發(fā)生器數(shù)據(jù)產(chǎn)生模塊設(shè)計
發(fā)布時間：2018-11-08 11:17
【摘要】：任意波形發(fā)生器基于直接數(shù)字合成技術(shù),是近年來發(fā)展迅速的一類信號源。憑借其輸出頻率分辨率高、頻率穩(wěn)定性強、能輸出用戶自定義復(fù)雜波形等優(yōu)勢,任意波形發(fā)生器被廣泛應(yīng)用于電子測試領(lǐng)域中。隨著電子技術(shù)的發(fā)展,測試任務(wù)中對激勵信號源的頻率帶寬、波形復(fù)雜度都提出了更高的要求。對任意波形發(fā)生器而言,采樣率和波形存儲深度是最基礎(chǔ)也是最重要的兩個參數(shù),這兩個參數(shù)決定了儀器輸出波形的質(zhì)量。如何提高采樣率以及存儲深度,成為任意波形發(fā)生器研究中的熱點和難點。針對上述背景,本文主要討論任意波形發(fā)生器中數(shù)據(jù)產(chǎn)生模塊的設(shè)計。該設(shè)計基于“4GSPS任意波形發(fā)生器”項目,功能是將所需生成波形數(shù)據(jù)進行存儲,并在波形合成過程中對波形數(shù)據(jù)進行高速尋址輸出,是直接決定任意波形發(fā)生器采樣率和存儲深度指標的關(guān)鍵設(shè)計。為實現(xiàn)設(shè)計目標,本文具體完成的工作如下:1.高速深存儲波形查找表設(shè)計。根據(jù)模塊的指標要求,論證了將DDR3 SDRAM作為波形查找表的可行性,重點分析了DDR3 SDRAM波形數(shù)據(jù)不連續(xù)以及讀取效率不穩(wěn)定的問題,并分別給出數(shù)據(jù)緩存方案以及高效讀取數(shù)據(jù)方法。最終在FPGA中完成數(shù)據(jù)跨時鐘域緩存、高速存儲器接口等邏輯設(shè)計,使波形數(shù)據(jù)產(chǎn)生模塊達到最高4GSPS采樣率數(shù)據(jù)產(chǎn)生速度,以及2G點的存儲深度要求。2.針對在生成復(fù)雜長周期信號時,波形存儲空間的利用效率低下的問題,分析了序列合成方法的原理和設(shè)計方案。結(jié)合DDR3 SDRAM的尋址特點,提出了一種基于指令方式的序列波地址發(fā)生器設(shè)計,該地址發(fā)生器具備靈活快速地對波形地址進行觸發(fā)、循環(huán)和跳轉(zhuǎn)等操作的能力,可以實現(xiàn)最大波形段長度64M點,段重復(fù)次數(shù)為1到616?10次的序列波形的合成輸出。3.測試和驗證。針對相應(yīng)功能和參數(shù)指標,制定測試方案并搭建測試平臺,通過對測試結(jié)果的分析,驗證模塊能以最高4GSPS采樣率產(chǎn)生各類常規(guī)波、任意波,并且實現(xiàn)了指定參數(shù)的觸發(fā)以及序列合成功能。
[Abstract]:Arbitrary waveform generator based on direct digital synthesis technology is a kind of signal source developed rapidly in recent years. With the advantages of high frequency resolution, strong frequency stability and the ability to output user-defined complex waveforms, arbitrary waveform generators are widely used in the field of electronic testing. With the development of electronic technology, the frequency bandwidth and waveform complexity of excitation signal source are required higher in the test task. For arbitrary waveform generator, sampling rate and waveform storage depth are the two most basic and important parameters, which determine the quality of the output waveform of the instrument. How to improve the sampling rate and storage depth has become a hot and difficult point in the research of arbitrary waveform generator. In view of the above background, this paper mainly discusses the design of data generation module in arbitrary waveform generator. The design is based on "4GSPS arbitrary Waveform Generator" project. The function of this design is to store the generated waveform data and to output the waveform data at high speed in the waveform synthesis process. It is a key design that directly determines the sampling rate and storage depth of arbitrary waveform generator. In order to achieve the design goal, the work accomplished in this paper is as follows: 1. High speed deep storage waveform lookup table design. According to the requirements of the module, the feasibility of using DDR3 SDRAM as a waveform lookup table is demonstrated. The problems of DDR3 SDRAM waveform data discontinuity and unstable reading efficiency are analyzed, and the data cache scheme and efficient data reading method are given respectively. Finally, the data across clock domain cache and high-speed memory interface are designed in FPGA to make the waveform data generation module achieve the maximum 4GSPS sampling rate data generation speed and the storage depth of 2G points. 2. Aiming at the inefficient use of waveform storage space in generating complex long-period signals, the principle and design scheme of sequence synthesis method are analyzed. According to the addressing characteristics of DDR3 SDRAM, a design of sequential wave address generator based on instruction is proposed. The address generator has the ability to trigger, cycle and jump the waveform address flexibly and quickly. The synthetic output of the sequence waveform with the maximum waveform length of 64m and the number of repeats of the segment between 1 and 616 ~ 10 times can be realized. 3. Test and verify. According to the corresponding function and parameter index, the test scheme is established and the test platform is built. Through the analysis of the test results, it is proved that the module can produce all kinds of conventional waves and arbitrary waves at the highest 4GSPS sampling rate. The trigger of specified parameters and the function of sequence synthesis are realized.
【學位授予單位】：電子科技大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN741
本文編號：2318325
[Abstract]:Arbitrary waveform generator based on direct digital synthesis technology is a kind of signal source developed rapidly in recent years. With the advantages of high frequency resolution, strong frequency stability and the ability to output user-defined complex waveforms, arbitrary waveform generators are widely used in the field of electronic testing. With the development of electronic technology, the frequency bandwidth and waveform complexity of excitation signal source are required higher in the test task. For arbitrary waveform generator, sampling rate and waveform storage depth are the two most basic and important parameters, which determine the quality of the output waveform of the instrument. How to improve the sampling rate and storage depth has become a hot and difficult point in the research of arbitrary waveform generator. In view of the above background, this paper mainly discusses the design of data generation module in arbitrary waveform generator. The design is based on "4GSPS arbitrary Waveform Generator" project. The function of this design is to store the generated waveform data and to output the waveform data at high speed in the waveform synthesis process. It is a key design that directly determines the sampling rate and storage depth of arbitrary waveform generator. In order to achieve the design goal, the work accomplished in this paper is as follows: 1. High speed deep storage waveform lookup table design. According to the requirements of the module, the feasibility of using DDR3 SDRAM as a waveform lookup table is demonstrated. The problems of DDR3 SDRAM waveform data discontinuity and unstable reading efficiency are analyzed, and the data cache scheme and efficient data reading method are given respectively. Finally, the data across clock domain cache and high-speed memory interface are designed in FPGA to make the waveform data generation module achieve the maximum 4GSPS sampling rate data generation speed and the storage depth of 2G points. 2. Aiming at the inefficient use of waveform storage space in generating complex long-period signals, the principle and design scheme of sequence synthesis method are analyzed. According to the addressing characteristics of DDR3 SDRAM, a design of sequential wave address generator based on instruction is proposed. The address generator has the ability to trigger, cycle and jump the waveform address flexibly and quickly. The synthetic output of the sequence waveform with the maximum waveform length of 64m and the number of repeats of the segment between 1 and 616 ~ 10 times can be realized. 3. Test and verify. According to the corresponding function and parameter index, the test scheme is established and the test platform is built. Through the analysis of the test results, it is proved that the module can produce all kinds of conventional waves and arbitrary waves at the highest 4GSPS sampling rate. The trigger of specified parameters and the function of sequence synthesis are realized.
【學位授予單位】：電子科技大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN741
【參考文獻】
相關(guān)期刊論文 前3條
1 張俊安;李廣軍;張瑞濤;楊毓軍;付東兵;;單片直接數(shù)字頻率合成器產(chǎn)品發(fā)展綜述[J];微電子學;2015年05期
2 丁寧;馬游春;秦麗;韓帥;;基于FPGA的DDR3-SDRAM控制器用戶接口設(shè)計[J];科學技術(shù)與工程;2014年17期
3 田書林;周鵬;劉科;;基于分相存儲和多DAC偽插值的高速波形合成方法[J];電子測量與儀器學報;2009年04期
相關(guān)博士學位論文 前1條
1 劉科;高速任意波形合成關(guān)鍵技術(shù)研究[D];電子科技大學;2010年
相關(guān)碩士學位論文 前7條
1 張銳敏;基于DDR2 SDRAM的任意波形發(fā)生模塊設(shè)計[D];電子科技大學;2013年
2 黃燕;基于FPGA的DDS信號發(fā)生器的研究[D];南京林業(yè)大學;2012年
3 黃云翔;DDR3 SDRAM控制器的設(shè)計和驗證[D];華南理工大學;2012年
4 王正宇;DDR3內(nèi)存控制器的IP核設(shè)計及FPGA驗證[D];蘭州交通大學;2012年
5 謝迪;500MSPS AWG序列模塊設(shè)計與波形發(fā)生模塊改進[D];電子科技大學;2009年
6 付江蔚;基于DDS信號發(fā)生器的研究和設(shè)計[D];電子科技大學;2007年
7 徐世偉;異步FIFO的設(shè)計與實現(xiàn)[D];西安電子科技大學;2007年
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