高速ADC的輸入輸出接口電路設(shè)計
發(fā)布時間：2018-11-04 09:51
【摘要】：隨著電子系統(tǒng)的工作頻率越來越高,無線通信、雷達、軟件無線電等應(yīng)用正在不斷地推動前端的A/D轉(zhuǎn)換器向射頻端靠攏,ADC的性能已經(jīng)成為制約整機性能提升的瓶頸,這其中的輸入輸出接口技術(shù)又是設(shè)計高性能ADC的重要環(huán)節(jié),成為了研究的熱點。論文首先,分析介紹了輸入信號完整性問題,圍繞其中的反射、串擾、信號抖動、EMI噪聲以及高頻信號的損耗等影響因素,分析了其形成原因并從電路模塊設(shè)計、器件尺寸大小、布局布線等方面給出了相應(yīng)的解決方案。其次,分析了輸入接口設(shè)計中需要考慮的因素,并據(jù)此開展了相應(yīng)的設(shè)計,這些因素包括輸入阻抗、輸入驅(qū)動電平、帶寬和通帶平坦度、信噪比和失真等。為應(yīng)對輸入信號完整性問題,設(shè)計了輸入阻抗匹配電路,包括其中的數(shù)字控制模塊、開關(guān)網(wǎng)絡(luò)、比較器等電路,實現(xiàn)了電阻的精準匹配,減小了信號的反射;為提高信號的線性度和帶寬,設(shè)計了輸入緩沖級電路,實現(xiàn)了信號的高速傳輸。論文基于TSMC 0.18μm CMOS工藝,利用Cadence Spectre進行電路設(shè)計和仿真。仿真結(jié)果表明:阻抗匹配電路可將電阻阻值穩(wěn)定在100Ω±1.43%;輸入緩沖級電路的SFDR為86.90dB,帶寬可達到3.6GHz,均達到設(shè)計要求。然后,分析了輸出接口電路的發(fā)展,并基于LVDS技術(shù)開展輸出接口電路的設(shè)計,包括驅(qū)動電路、共模反饋電路、基準電路和緩沖電路等,設(shè)計時考慮了功耗、面積、性能等多方面因素,增加了預(yù)充放電技術(shù)、負反饋鉗位技術(shù)以及偏斜調(diào)整技術(shù)等等。論文對設(shè)計的輸出接口電路進行了仿真,仿真結(jié)果表明,在輸入信號為1GHz的速率、電源電壓為1.8V的工作條件下,LVDS輸出信號穩(wěn)定在共模電平上下300mV左右,且占空比達到48%,滿足設(shè)計要求。最后,根據(jù)版圖設(shè)計規(guī)則,分析了設(shè)計過程中可能遇到的一些問題,如串擾、噪聲、匹配以及閂鎖效應(yīng)和天線效應(yīng)等,并給出了相應(yīng)的解決方案,完成了 LVDS輸出接口電路版圖的設(shè)計與驗證。
[Abstract]:With the increasing frequency of electronic system, wireless communication, radar, software radio and other applications are constantly promoting the front end of the A / D converter to the RF end, the performance of ADC has become a bottleneck restricting the performance of the whole machine. The input-output interface technology is an important part of designing high-performance ADC and has become a hot research topic. First of all, the paper introduces the integrity of input signal, including reflection, crosstalk, signal jitter, EMI noise and the loss of high frequency signal, analyzes the reasons of its formation, and designs the circuit module from the point of view of the reflection, crosstalk, signal jitter, EMI noise and the loss of high frequency signal. The corresponding solutions are given in terms of device size, layout and wiring. Secondly, the factors that need to be considered in the design of the input interface are analyzed, and the corresponding design is carried out. These factors include input impedance, input driving level, bandwidth and passband flatness, signal-to-noise ratio and distortion and so on. In order to deal with the problem of input signal integrity, the input impedance matching circuit is designed, including digital control module, switch network, comparator and so on, which realizes the accurate matching of resistance and reduces the reflection of signal. In order to improve the linearity and bandwidth of the signal, the input buffer level circuit is designed, and the high-speed transmission of the signal is realized. Based on TSMC 0.18 渭 m CMOS process, the circuit is designed and simulated by Cadence Spectre. The simulation results show that the impedance matching circuit can stabilize the resistance value to 100 惟 鹵1.43 and the SFDR of the input buffer circuit is 86.90 dB, and the bandwidth can reach 3.6 GHz, all of which meet the design requirements. Then, the development of output interface circuit is analyzed, and the design of output interface circuit based on LVDS technology is carried out, including drive circuit, common-mode feedback circuit, reference circuit and buffer circuit. Many factors, such as performance, precharge and discharge technology, negative feedback clamp technology and skew adjustment technology are added. The output interface circuit is simulated in this paper. The simulation results show that under the condition that the input signal is 1GHz and the power supply voltage is 1.8 V, the output signal of LVDS is stable at the common mode level about 300mV. And duty cycle up to 48, meet the design requirements. Finally, according to the layout design rules, some possible problems in the design process, such as crosstalk, noise, matching, latch effect and antenna effect, are analyzed, and the corresponding solutions are given. The layout of LVDS output interface circuit is designed and verified.
【學(xué)位授予單位】：合肥工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TN792
[Abstract]:With the increasing frequency of electronic system, wireless communication, radar, software radio and other applications are constantly promoting the front end of the A / D converter to the RF end, the performance of ADC has become a bottleneck restricting the performance of the whole machine. The input-output interface technology is an important part of designing high-performance ADC and has become a hot research topic. First of all, the paper introduces the integrity of input signal, including reflection, crosstalk, signal jitter, EMI noise and the loss of high frequency signal, analyzes the reasons of its formation, and designs the circuit module from the point of view of the reflection, crosstalk, signal jitter, EMI noise and the loss of high frequency signal. The corresponding solutions are given in terms of device size, layout and wiring. Secondly, the factors that need to be considered in the design of the input interface are analyzed, and the corresponding design is carried out. These factors include input impedance, input driving level, bandwidth and passband flatness, signal-to-noise ratio and distortion and so on. In order to deal with the problem of input signal integrity, the input impedance matching circuit is designed, including digital control module, switch network, comparator and so on, which realizes the accurate matching of resistance and reduces the reflection of signal. In order to improve the linearity and bandwidth of the signal, the input buffer level circuit is designed, and the high-speed transmission of the signal is realized. Based on TSMC 0.18 渭 m CMOS process, the circuit is designed and simulated by Cadence Spectre. The simulation results show that the impedance matching circuit can stabilize the resistance value to 100 惟 鹵1.43 and the SFDR of the input buffer circuit is 86.90 dB, and the bandwidth can reach 3.6 GHz, all of which meet the design requirements. Then, the development of output interface circuit is analyzed, and the design of output interface circuit based on LVDS technology is carried out, including drive circuit, common-mode feedback circuit, reference circuit and buffer circuit. Many factors, such as performance, precharge and discharge technology, negative feedback clamp technology and skew adjustment technology are added. The output interface circuit is simulated in this paper. The simulation results show that under the condition that the input signal is 1GHz and the power supply voltage is 1.8 V, the output signal of LVDS is stable at the common mode level about 300mV. And duty cycle up to 48, meet the design requirements. Finally, according to the layout design rules, some possible problems in the design process, such as crosstalk, noise, matching, latch effect and antenna effect, are analyzed, and the corresponding solutions are given. The layout of LVDS output interface circuit is designed and verified.
【學(xué)位授予單位】：合肥工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TN792
【參考文獻】
相關(guān)期刊論文 前10條
1 王俊博;;10位SAR ADC的版圖設(shè)計[J];通訊世界;2015年18期
2 朱曉宇;居水榮;;一種應(yīng)用于ADC帶曲率補償?shù)母呔葞痘鶞试碵J];現(xiàn)代電子技術(shù);2015年02期
3 彭宣霖;李航標;陳劍洛;王新宇;付松林;羅萍;;一種高速低功耗動態(tài)比較器設(shè)計[J];微電子學(xué);2014年05期
4 陳麗;;傳輸線信號完整性的反射分析[J];工礦自動化;2014年03期
5 吳慶軒;李秋俊;;0.18μm CMOS單電流源模式LVDS驅(qū)動器設(shè)計[J];微電子學(xué);2013年05期
6 王翠珍;王春雷;唐金元;;自動阻抗匹配網(wǎng)絡(luò)的設(shè)計與實現(xiàn)[J];儀表技術(shù);2013年05期
7 李鵬;徐東明;張翔禎;;一種基于柵交叉耦合連接的電荷泵設(shè)計[J];中國集成電路;2012年08期
8 馬磊;原義棟;張海峰;;一種改進的增益增強共源共柵放大器的設(shè)計[J];現(xiàn)代電子技術(shù);2011年10期
9 李偉偉;劉輝華;徐小良;;一種具有共模反饋的低抖動LVDS驅(qū)動器[J];微電子學(xué)與計算機;2011年01期
10 吳允平;蘇偉達;李汪彪;蔡聲鎮(zhèn);;電路系統(tǒng)中的閂鎖效應(yīng)及其預(yù)防設(shè)計[J];現(xiàn)代電子技術(shù);2011年01期
相關(guān)博士學(xué)位論文 前2條
1 蔡化;無校準低功耗12位100MS/s ADC的設(shè)計與實現(xiàn)[D];電子科技大學(xué);2015年
2 沈s，
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