硅通孔焊點熱疲勞壽命估算及不確定性研究
發(fā)布時間：2018-10-31 20:04
【摘要】：隨著市場對產(chǎn)品功能的需求不斷提升,傳統(tǒng)的二維電子封裝技術(shù)遇到的瓶頸問題越來越突出,三維集成技術(shù)逐漸成為主流。硅通孔技術(shù)(Through Silicon Via,TSV)即通過在芯片間和晶圓間的垂直通孔中填充導(dǎo)體,進而實現(xiàn)芯片互連。這種芯片互連方式突出優(yōu)點是封裝體體積小、性能強、信號傳遞速度快,缺點是整體散熱能力降低。這使得TSV技術(shù)面臨的最主要挑戰(zhàn)依然集中在與熱相關(guān)的失效問題上。另外,在集成電路封裝設(shè)計工作中廣泛應(yīng)用的是基于確定性參數(shù)的數(shù)值仿真手段。但事實上,任何實際結(jié)構(gòu)都存在不同程度的不確定性,將不確定問題作為確定性問題來計算,得到的結(jié)果會過于保守,區(qū)間分析方法為解決這類問題提供了一條路徑。針對TSV技術(shù)封裝組件中焊點的熱失效問題,本文開展了封裝組件熱力耦合問題相關(guān)研究工作,主要內(nèi)容包含如下幾個方面:1、選取基于TSV技術(shù)互連的結(jié)構(gòu)模型,利用ANSYS有限元軟件建立起簡化的二維數(shù)值模型并進行熱力耦合計算,參照JEDEC標(biāo)準(zhǔn)溫度載荷,用粘塑性本構(gòu)Anand方程來描述SnPb釬料焊點的力學(xué)行為。根據(jù)模型的溫度場、應(yīng)力/應(yīng)變場的結(jié)果發(fā)現(xiàn)危險焊點位置,利用Engelmaier提出的修正Coffin-Manson經(jīng)驗方程估算危險焊點的熱疲勞壽命,以便進行產(chǎn)品可靠性的預(yù)測。2、探討改變單一參量值包括芯片大小、芯片層數(shù)、基板厚度以及通孔直徑、通孔深度、通孔間距對焊點的熱疲勞壽命的影響。記錄每列焊點溫度、應(yīng)力、應(yīng)變等數(shù)據(jù)并擬合出變化曲線,計算比較各參量值對焊點的疲勞壽命的影響程度,總結(jié)出焊點疲勞壽命隨所選參量的變化規(guī)律,得到的結(jié)論為相關(guān)設(shè)計與優(yōu)化工作提供理論參考。3、針對TSV模型結(jié)構(gòu)在實際制作過程中存在大量不確定因素的現(xiàn)實,考慮將熱物性參數(shù)等不確定參數(shù)作為區(qū)間變量,主要結(jié)合有限元法和區(qū)間分析法,對TSV結(jié)構(gòu)熱傳導(dǎo)問題進行區(qū)間不確定分析。通過對TSV模型進行確定參數(shù)的熱力耦合計算以及具有不確定參數(shù)的區(qū)間分析,得到模型結(jié)構(gòu)尺寸參數(shù)和構(gòu)成材料的物理參數(shù)對焊點疲勞壽命的影響規(guī)律,為電子封裝熱問題的研究提供了有價值的參考。
[Abstract]:With the increasing demand for product function in the market, the bottleneck of traditional two-dimensional electronic packaging technology is becoming more and more prominent, and three-dimensional integration technology is gradually becoming the mainstream. Silicon through hole technology (Through Silicon Via,TSV) is to interconnect chips by filling the vertical holes between chips and wafers. The advantages of this kind of chip interconnection are small size, strong performance, fast signal transfer speed and low overall heat dissipation ability. This makes the main challenge for TSV technology to remain focused on thermal-related failures. In addition, the numerical simulation method based on deterministic parameters is widely used in IC package design. But in fact, any real structure has different degree of uncertainty, and the result of the uncertain problem as a deterministic problem will be too conservative. The interval analysis method provides a way to solve this kind of problem. Aiming at the thermal failure problem of solder joint in TSV encapsulation assembly, this paper has carried out the research work related to the thermal coupling problem of package assembly. The main contents include the following aspects: 1. The structural model based on TSV technology interconnection is selected. A simplified two-dimensional numerical model was established by using ANSYS finite element software, and the mechanical behavior of solder joint of SnPb solder was described by viscoplastic constitutive Anand equation with reference to the standard temperature load of JEDEC. According to the results of temperature field and stress / strain field of the model, the location of dangerous solder joint is found. The thermal fatigue life of dangerous solder joint is estimated by using the modified Coffin-Manson empirical equation proposed by Engelmaier in order to predict the reliability of product. The influence of changing single parameter value including chip size, chip layer number, substrate thickness, through hole diameter, through hole depth and through hole spacing on thermal fatigue life of solder joint is discussed. The data of solder joint temperature, stress and strain in each column were recorded and the curve was fitted. The influence of each parameter on the fatigue life of solder joint was calculated and compared, and the variation of fatigue life of solder joint with the selected parameters was summarized. The conclusion provides a theoretical reference for the related design and optimization work. 3. In view of the fact that there are a lot of uncertain factors in the process of making TSV model structure, the uncertain parameters such as thermal physical properties are considered as interval variables. Combined with finite element method and interval analysis method, the interval uncertainty analysis of heat conduction problem of TSV structure is carried out. Based on the thermodynamic coupling calculation of the TSV model and the interval analysis with uncertain parameters, the influence of the structural parameters of the model and the physical parameters of the material on the fatigue life of the solder joint is obtained. It provides a valuable reference for the thermal research of electronic packaging.
【學(xué)位授予單位】：大連交通大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN405
本文編號：2303388
[Abstract]:With the increasing demand for product function in the market, the bottleneck of traditional two-dimensional electronic packaging technology is becoming more and more prominent, and three-dimensional integration technology is gradually becoming the mainstream. Silicon through hole technology (Through Silicon Via,TSV) is to interconnect chips by filling the vertical holes between chips and wafers. The advantages of this kind of chip interconnection are small size, strong performance, fast signal transfer speed and low overall heat dissipation ability. This makes the main challenge for TSV technology to remain focused on thermal-related failures. In addition, the numerical simulation method based on deterministic parameters is widely used in IC package design. But in fact, any real structure has different degree of uncertainty, and the result of the uncertain problem as a deterministic problem will be too conservative. The interval analysis method provides a way to solve this kind of problem. Aiming at the thermal failure problem of solder joint in TSV encapsulation assembly, this paper has carried out the research work related to the thermal coupling problem of package assembly. The main contents include the following aspects: 1. The structural model based on TSV technology interconnection is selected. A simplified two-dimensional numerical model was established by using ANSYS finite element software, and the mechanical behavior of solder joint of SnPb solder was described by viscoplastic constitutive Anand equation with reference to the standard temperature load of JEDEC. According to the results of temperature field and stress / strain field of the model, the location of dangerous solder joint is found. The thermal fatigue life of dangerous solder joint is estimated by using the modified Coffin-Manson empirical equation proposed by Engelmaier in order to predict the reliability of product. The influence of changing single parameter value including chip size, chip layer number, substrate thickness, through hole diameter, through hole depth and through hole spacing on thermal fatigue life of solder joint is discussed. The data of solder joint temperature, stress and strain in each column were recorded and the curve was fitted. The influence of each parameter on the fatigue life of solder joint was calculated and compared, and the variation of fatigue life of solder joint with the selected parameters was summarized. The conclusion provides a theoretical reference for the related design and optimization work. 3. In view of the fact that there are a lot of uncertain factors in the process of making TSV model structure, the uncertain parameters such as thermal physical properties are considered as interval variables. Combined with finite element method and interval analysis method, the interval uncertainty analysis of heat conduction problem of TSV structure is carried out. Based on the thermodynamic coupling calculation of the TSV model and the interval analysis with uncertain parameters, the influence of the structural parameters of the model and the physical parameters of the material on the fatigue life of the solder joint is obtained. It provides a valuable reference for the thermal research of electronic packaging.
【學(xué)位授予單位】：大連交通大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN405
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