HS32K芯片工程批流片的后端實現(xiàn)
發(fā)布時間：2018-10-26 15:14
【摘要】：在集成電路迅猛發(fā)展的今天,SOC芯片逐漸成為業(yè)界的焦點。SOC設(shè)計流程主要是從前端設(shè)計到后端實現(xiàn),設(shè)計周期一般都會很長。前端設(shè)計主要包括RTL代碼的編譯;門級網(wǎng)表綜合;靜態(tài)時序分析。后端實現(xiàn)主要包括整體布局布線;功耗分析;物理驗證。如今工藝尺寸已經(jīng)進(jìn)入超深亞微米階段。時間延遲、信號完整性、天線效應(yīng)等問題已經(jīng)越發(fā)嚴(yán)重,它們制約著當(dāng)今集成電路的發(fā)展。本文針對上述三個問題進(jìn)行了深入研究,提出了解決方案并且成功應(yīng)用到了HS32K芯片的物理設(shè)計中。HS32K芯片采用HJTC的110nm工藝,工作電壓為1.5V,工作電流為30m A。論文主要通過Design Compiler、IC Compiler、Prime Time等工具分析時序、功耗、擁塞度等各方面問題。本文基于HS32K芯片的物理設(shè)計,介紹了該款芯片后端實現(xiàn)的整體流程。對物理環(huán)境建立、布局規(guī)劃、IO和標(biāo)準(zhǔn)單元布局、時鐘樹綜合、布線設(shè)計等關(guān)鍵步驟作出了詳細(xì)分析�；趥鹘y(tǒng)方法進(jìn)行靜態(tài)時序分析,對每個關(guān)鍵步驟的時序都嚴(yán)格驗證。在時鐘樹綜合之后,采用useful_skew修復(fù)建立時間違例。得到GDSII文件和網(wǎng)表文件后,通過時序、預(yù)期功能的檢驗;DRC、LVS檢查并完成天線效應(yīng)的修復(fù)。最終實現(xiàn)HS32K的工程批流片。本文中的主要工作包括如下:在時鐘樹綜合之后,大膽采用useful_skew方法修復(fù)建立時間違例,得到了很好的效果。布線完成后,仍有兩條shorting問題,切除附近少許電源網(wǎng)格來增加布線通道,利用IC Compiler工具自動繞線,成功修復(fù)了這兩條shorting問題。
[Abstract]:With the rapid development of integrated circuits, SOC chips have gradually become the focus of the industry. The design process of SOC is mainly from front-end design to back-end implementation, and the design cycle is usually very long. Front-end design mainly includes RTL code compilation, gate network table synthesis, static timing analysis. The back-end implementation mainly includes overall layout and routing, power analysis and physical verification. Now the process size has entered the ultra-deep sub-micron stage. The problems of time delay, signal integrity and antenna effect have become more and more serious, which restrict the development of integrated circuits. In this paper, the above three problems are deeply studied, and the solution is put forward and successfully applied to the physical design of HS32K chip. The HS32K chip adopts the 110nm technology of HJTC, the working voltage is 1.5V and the working current is 30mA. In this paper, Design Compiler,IC Compiler,Prime Time and other tools are used to analyze timing, power consumption, congestion and other problems. Based on the physical design of the HS32K chip, this paper introduces the whole process of the backend implementation of the chip. The key steps such as physical environment establishment, layout planning, IO and standard cell layout, clock tree synthesis, routing design and so on are analyzed in detail. The static timing analysis based on the traditional method is verified strictly for each key step. After clock tree synthesis, useful_skew is used to repair the time violation. After the GDSII file and the network table file are obtained, the time sequence and expected function are checked, and the antenna effect is checked and repaired by DRC,LVS. Finally, the project batch flow sheet of HS32K is realized. The main work of this paper is as follows: after clock tree synthesis, useful_skew method is used to repair the establishment time violation and good results are obtained. After wiring is completed, there are still two shorting problems. The two shorting problems are successfully repaired by removing a few power grids nearby to increase the wiring channel and using the IC Compiler tool to automatically wrap the wire.
【學(xué)位授予單位】：遼寧大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN405
本文編號：2296132
[Abstract]:With the rapid development of integrated circuits, SOC chips have gradually become the focus of the industry. The design process of SOC is mainly from front-end design to back-end implementation, and the design cycle is usually very long. Front-end design mainly includes RTL code compilation, gate network table synthesis, static timing analysis. The back-end implementation mainly includes overall layout and routing, power analysis and physical verification. Now the process size has entered the ultra-deep sub-micron stage. The problems of time delay, signal integrity and antenna effect have become more and more serious, which restrict the development of integrated circuits. In this paper, the above three problems are deeply studied, and the solution is put forward and successfully applied to the physical design of HS32K chip. The HS32K chip adopts the 110nm technology of HJTC, the working voltage is 1.5V and the working current is 30mA. In this paper, Design Compiler,IC Compiler,Prime Time and other tools are used to analyze timing, power consumption, congestion and other problems. Based on the physical design of the HS32K chip, this paper introduces the whole process of the backend implementation of the chip. The key steps such as physical environment establishment, layout planning, IO and standard cell layout, clock tree synthesis, routing design and so on are analyzed in detail. The static timing analysis based on the traditional method is verified strictly for each key step. After clock tree synthesis, useful_skew is used to repair the time violation. After the GDSII file and the network table file are obtained, the time sequence and expected function are checked, and the antenna effect is checked and repaired by DRC,LVS. Finally, the project batch flow sheet of HS32K is realized. The main work of this paper is as follows: after clock tree synthesis, useful_skew method is used to repair the establishment time violation and good results are obtained. After wiring is completed, there are still two shorting problems. The two shorting problems are successfully repaired by removing a few power grids nearby to increase the wiring channel and using the IC Compiler tool to automatically wrap the wire.
【學(xué)位授予單位】：遼寧大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN405
【參考文獻(xiàn)】
相關(guān)期刊論文 前2條
1 周平,戴慶元;芯片設(shè)計中串?dāng)_噪聲的分析與改善[J];半導(dǎo)體技術(shù);2004年01期
2 時昕,王東輝,侯朝煥;深亞微米SoC中的電源/地網(wǎng)絡(luò)設(shè)計[J];微電子學(xué)與計算機;2004年12期
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