【摘要】：針對(duì)帶隙基準(zhǔn)的精度會(huì)影響集成電路的性能問(wèn)題,提出了一種新的帶隙基準(zhǔn)電路結(jié)構(gòu).通過(guò)采用負(fù)反饋補(bǔ)償網(wǎng)絡(luò)來(lái)增強(qiáng)電源抑制比,降低失調(diào)電壓,從而提高了電路的穩(wěn)定性和精度.基于SMIC 0.18μm 1.8V CMOS工藝,利用Cadence spectre仿真,結(jié)果表明:在-30℃~100℃溫度范圍內(nèi),溫漂系數(shù)為34.6×10~(-6)/℃;低頻下電源抑制比為-63.5dB;功耗僅1.5μW.該電路適用于低壓低功耗能量獲取系統(tǒng).
[Abstract]:Aiming at the problem that the precision of bandgap reference affects the performance of integrated circuit, a new band-gap reference circuit structure is proposed. The negative feedback compensation network is used to enhance the power supply rejection ratio and reduce the offset voltage, thus improving the stability and accuracy of the circuit. Based on SMIC 0.18 渭 m 1.8V CMOS process and Cadence spectre simulation, the results show that the temperature drift coefficient is 34.6 脳 10 ~ (-6) / 鈩，

本文編號(hào)：2295172