600V高雪崩耐量平面柵VDMOS器件優(yōu)化設(shè)計(jì)
發(fā)布時(shí)間：2018-10-25 20:54
【摘要】：功率MOSFET器件作為能源管理的核心控制單元,由于具有良好的電學(xué)特性和低廉的成本,因而廣泛應(yīng)用在汽車電子、消費(fèi)電子以及航空航天等領(lǐng)域。目前在高端市場的應(yīng)用領(lǐng)域里,國外的半導(dǎo)體公司仍然占據(jù)主導(dǎo),國內(nèi)的VDMOS設(shè)計(jì)與制造技術(shù)處于落后地位,特別是器件的雪崩耐量低、可靠性差等問題。雖然國內(nèi)外對(duì)于雪崩耐量的理論研究已經(jīng)比較成熟,但是提出一種架構(gòu)合理、生產(chǎn)成本低廉的雪崩耐量加固方案依然非常困難。本論文是基于本實(shí)驗(yàn)小組與國內(nèi)某著名半導(dǎo)體制造商的合作課題,主要目的是研發(fā)一款具有高雪崩耐量的600V平面柵VDMOS器件,籍此推動(dòng)高性能VDMOS的國產(chǎn)化。本論文的主要內(nèi)容如下:首先介紹了VDMOS器件設(shè)計(jì)的理論基礎(chǔ)和雪崩耐量的加固方法。接著研究不同器件的結(jié)構(gòu)與特點(diǎn),選取合適的元胞和終端結(jié)構(gòu),并根據(jù)實(shí)際工藝提出VDMOS器件可行的工藝流程方案�；赥suprem4/Medici仿真軟件,通過優(yōu)化工藝條件以及元胞尺寸,得到基本的元胞參數(shù)設(shè)計(jì),針對(duì)影響雪崩耐量的關(guān)鍵因素,并提出H型N~+接觸孔的版圖設(shè)計(jì)方案,進(jìn)一步提升器件的雪崩耐量。接著進(jìn)行VDMOS器件終端的仿真優(yōu)化設(shè)計(jì)。首先選取JTE終端結(jié)構(gòu),利用軟件Tsuprem4/Medici,仿真得到峰值電場小于2×10~5 V/cm,耐壓大小滿足設(shè)計(jì)規(guī)范的結(jié)果。接著采用先進(jìn)的高溫推阱工藝,設(shè)計(jì)了VLD終端結(jié)構(gòu),仿真得到峰值電場小于1.8×10~5 V/cm、擊穿穩(wěn)定性更好的結(jié)果。最后利用Candence軟件完成版圖繪制,成功流片。對(duì)流片樣品的靜態(tài)參數(shù)和雪崩電流進(jìn)行測試,第一次流片結(jié)果表明,擊穿電壓大于640V,閾值為3V,導(dǎo)通電阻為1.75Ω,雪崩耐量低于0.1A。其后更改了工藝流程,并且重新流片,第二次流片測試結(jié)果表明,兩種元胞結(jié)構(gòu)的雪崩電流分別為2.1A、2.5A,可知通過改進(jìn)版圖和工藝設(shè)計(jì),雪崩耐量能得到顯著提高。
[Abstract]:As the core control unit of energy management, power MOSFET devices are widely used in automotive electronics, consumer electronics, aerospace and other fields because of their good electrical properties and low cost. At present, in the application field of high-end market, foreign semiconductor companies still dominate, and domestic VDMOS design and manufacturing technology is in a backward position, especially the problems of low avalanche tolerance and poor reliability of devices. Although the theoretical research on avalanche tolerance has been mature at home and abroad, it is still very difficult to propose an avalanche tolerance reinforcement scheme with reasonable structure and low production cost. This paper is based on the research work of this experiment group and a famous semiconductor manufacturer in China. The main purpose of this paper is to develop a 600V planar gate VDMOS device with high avalanche tolerance to promote the localization of high performance VDMOS. The main contents of this thesis are as follows: firstly, the theoretical basis of VDMOS device design and the strengthening method of avalanche tolerance are introduced. Then, the structure and characteristics of different devices are studied, and the appropriate cellular and terminal structures are selected, and the feasible technological process of VDMOS devices is put forward according to the actual process. Based on Tsuprem4/Medici simulation software, the basic cell parameter design is obtained by optimizing the process conditions and cell size. Aiming at the key factors affecting the avalanche tolerance, the layout design scheme of H type N- contact hole is proposed. Further improve the avalanche tolerance of the device. Then the simulation optimization design of VDMOS device terminal is carried out. Firstly, the JTE terminal structure is selected, and the peak electric field is less than 2 脳 10 ~ 5 V / cm by software Tsuprem4/Medici, simulation. Then the VLD terminal structure is designed by using advanced high-temperature push-well technology. The simulation results show that the peak electric field is less than 1.8 脳 10 ~ (5) V / cm, and the breakdown stability is better. Finally, using Candence software to complete the layout drawing, successful flow. The static parameters and avalanche current of the sample were measured. The results of the first flowsheet show that the breakdown voltage is greater than 640 V, the threshold is 3 V, the on-resistance is 1.75 惟, and the avalanche tolerance is less than 0.1 A. Then the technological process was changed and the flow sheet was reflow. The results of the second flowsheet test showed that the avalanche current of the two cellular structures was 2.1A ~ (2. 5) A, respectively. It can be seen that the avalanche tolerance can be improved significantly by improving the layout and the technological design.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN386
本文編號(hào)：2294812
[Abstract]:As the core control unit of energy management, power MOSFET devices are widely used in automotive electronics, consumer electronics, aerospace and other fields because of their good electrical properties and low cost. At present, in the application field of high-end market, foreign semiconductor companies still dominate, and domestic VDMOS design and manufacturing technology is in a backward position, especially the problems of low avalanche tolerance and poor reliability of devices. Although the theoretical research on avalanche tolerance has been mature at home and abroad, it is still very difficult to propose an avalanche tolerance reinforcement scheme with reasonable structure and low production cost. This paper is based on the research work of this experiment group and a famous semiconductor manufacturer in China. The main purpose of this paper is to develop a 600V planar gate VDMOS device with high avalanche tolerance to promote the localization of high performance VDMOS. The main contents of this thesis are as follows: firstly, the theoretical basis of VDMOS device design and the strengthening method of avalanche tolerance are introduced. Then, the structure and characteristics of different devices are studied, and the appropriate cellular and terminal structures are selected, and the feasible technological process of VDMOS devices is put forward according to the actual process. Based on Tsuprem4/Medici simulation software, the basic cell parameter design is obtained by optimizing the process conditions and cell size. Aiming at the key factors affecting the avalanche tolerance, the layout design scheme of H type N- contact hole is proposed. Further improve the avalanche tolerance of the device. Then the simulation optimization design of VDMOS device terminal is carried out. Firstly, the JTE terminal structure is selected, and the peak electric field is less than 2 脳 10 ~ 5 V / cm by software Tsuprem4/Medici, simulation. Then the VLD terminal structure is designed by using advanced high-temperature push-well technology. The simulation results show that the peak electric field is less than 1.8 脳 10 ~ (5) V / cm, and the breakdown stability is better. Finally, using Candence software to complete the layout drawing, successful flow. The static parameters and avalanche current of the sample were measured. The results of the first flowsheet show that the breakdown voltage is greater than 640 V, the threshold is 3 V, the on-resistance is 1.75 惟, and the avalanche tolerance is less than 0.1 A. Then the technological process was changed and the flow sheet was reflow. The results of the second flowsheet test showed that the avalanche current of the two cellular structures was 2.1A ~ (2. 5) A, respectively. It can be seen that the avalanche tolerance can be improved significantly by improving the layout and the technological design.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN386
【參考文獻(xiàn)】
相關(guān)期刊論文 前7條
1 趙圣哲;李理;趙文魁;;VDMOS結(jié)終端技術(shù)對(duì)比研究[J];半導(dǎo)體技術(shù);2016年01期
2 胡強(qiáng);王思亮;張世勇;;從功率半導(dǎo)體器件發(fā)展看電力電子技術(shù)未來[J];東方電氣評(píng)論;2015年03期
3 孫偉鋒;張波;肖勝安;蘇巍;成建兵;;功率半導(dǎo)體器件與功率集成技術(shù)的發(fā)展現(xiàn)狀及展望[J];中國科學(xué):信息科學(xué);2012年12期
4 馬萬里;趙文魁;;VDMOS的UIS能力與制造工藝流程的關(guān)系[J];微電子學(xué);2012年02期
5 陳文高;荊吉利;孫偉鋒;;半超結(jié)VDMOS的研究[J];微電子學(xué);2009年04期
6 張娜;吳曉鵬;亢寶位;;溝槽柵低壓功率MOSFET的發(fā)展(下)——減小優(yōu)值FoM[J];電力電子;2004年04期
7 陳星弼;MOS型功率器件[J];電子學(xué)報(bào);1990年05期
相關(guān)碩士學(xué)位論文 前4條
1 許高潮;一種具有VLD終端結(jié)構(gòu)的600V VDMOS設(shè)計(jì)[D];電子科技大學(xué);2015年
2 鄧光敏;采用挖槽填充工藝的DMOS的雪崩耐量研究[D];電子科技大學(xué);2013年
3 婁靖超;功率MOSFET的UIS特性研究[D];電子科技大學(xué);2009年
4 顧曉健;關(guān)于改善功率MOSFET器件的UIS測試能力的方法研究[D];上海交通大學(xué);2008年
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