【摘要】：隨著空間儀器所承擔(dān)任務(wù)的復(fù)雜性與精密性逐步提升,具備高性能,低成本和可重配置等優(yōu)勢(shì)的SRAM型FPGA在空間儀器中的應(yīng)用也越來(lái)越多,這給空間儀器帶來(lái)性能上提升的同時(shí)也引來(lái)了諸多問(wèn)題,其中單粒子效應(yīng)造成的影響尤為突出,且隨著集成電路特征尺寸的逐漸減少,這一影響還會(huì)越來(lái)越嚴(yán)重。對(duì)FPGA系統(tǒng)單粒子軟錯(cuò)誤敏感性的分析能夠找到FPGA系統(tǒng)中受單粒子效應(yīng)影響最為嚴(yán)重的地方,抓住設(shè)計(jì)中抗單粒子軟錯(cuò)誤的薄弱環(huán)節(jié)。如此,在地面即可預(yù)言系統(tǒng)在軌的運(yùn)行情況,有針對(duì)性的進(jìn)行系統(tǒng)加固和制定應(yīng)對(duì)措施,保證系統(tǒng)的正常運(yùn)行。目前業(yè)內(nèi)公認(rèn)的評(píng)估器件單粒子軟錯(cuò)誤敏感性的方法為高能粒子實(shí)驗(yàn)和故障注入,前者成本高昂,資源緊張,后者注入時(shí)間長(zhǎng),效率低。本文研究的基于XDL網(wǎng)表的SRAM型FPGA單粒子軟錯(cuò)誤敏感性分析方法,能夠快速高效的分析系統(tǒng)單粒子軟錯(cuò)誤,且成本低廉,是未來(lái)評(píng)估系統(tǒng)單粒子軟錯(cuò)誤敏感性的重要手段。研究將從Xilinx FPGA設(shè)計(jì)中得到的.ncd文件出發(fā),得到XDL網(wǎng)表,再基于Rapidsmith開發(fā)用于提取電路結(jié)構(gòu)信息,進(jìn)行系統(tǒng)單粒子軟錯(cuò)誤敏感性分析的軟件。論文研究主要工作包括:(1)敏感點(diǎn)的判斷方法。論文研究的敏感點(diǎn)的判斷方法可以把敏感點(diǎn)定位到具體的每一個(gè)配置位,具有更高準(zhǔn)確度,并基于Rapidsmith開發(fā)了XDL網(wǎng)表的分析軟件,目前支持XC4VSX55 FPGA系統(tǒng)的單粒子軟錯(cuò)誤敏感性分析。(2)XDL網(wǎng)表中FPGA資源的解析。論文研究了XDL網(wǎng)表描述的FPGA資源,解讀了敏感資源在XDL網(wǎng)表中的描述,闡述了XDL網(wǎng)表的語(yǔ)法結(jié)構(gòu)、詳細(xì)解析了其描述內(nèi)容和FPGA的底層電路資源的對(duì)應(yīng)關(guān)系,強(qiáng)化了人們對(duì)XDL網(wǎng)表與FPGA資源的認(rèn)知,彌補(bǔ)了國(guó)內(nèi)此類內(nèi)容描述不清的缺點(diǎn)。(3)配置文件中FPGA資源的解析。論文完成了XDL網(wǎng)表描述的FPGA資源與配置位的映射關(guān)系,糾正了Xilinx官網(wǎng)上發(fā)布的XC4VSX55芯片幀地址排布的錯(cuò)誤,并進(jìn)一步探究了PIPs資源與配置位的對(duì)應(yīng)關(guān)系,解析了幀結(jié)構(gòu),基本完成了XC4VSX55芯片配置數(shù)據(jù)的解析,且研究方法具有通用性,適用于Virtex-5及更高系列芯片。
[Abstract]:With the increasing complexity and precision of space instruments, SRAM type FPGA, which has the advantages of high performance, low cost and reconfiguration, has been used more and more in space instruments. While improving the performance of space instruments, it also leads to many problems, among which the effect of single particle effect is especially prominent, and the effect will become more and more serious with the decreasing of the feature size of integrated circuits. By analyzing the sensitivity of single particle soft error in FPGA system, we can find out the most serious effect of single particle effect in FPGA system, and grasp the weak link in the design against single particle soft error. In this way, the operation of the system in orbit can be predicted on the ground, and the system reinforcement and countermeasures can be made to ensure the normal operation of the system. At present, high-energy particle experiments and fault injection are widely used to evaluate the sensitivity of single particle soft error in devices. The former is costly and the resources are tight, while the latter has long injection time and low efficiency. The sensitivity analysis method of single particle soft error of SRAM type FPGA based on XDL net table is studied in this paper. It can analyze single particle soft error of system quickly and efficiently, and the cost is low. It is an important method to evaluate the sensitivity of single particle soft error of system in the future. Starting from the. Ncd file obtained from the Xilinx FPGA design, the paper obtains the XDL net table, and then develops a software based on Rapidsmith to extract the circuit structure information and analyze the sensitivity of the single particle soft error in the system. The main work of this paper is as follows: (1) the judgment method of sensitive points. The judgment method of sensitive points studied in this paper can locate the sensitive points to every configuration bit and have higher accuracy. The analysis software of XDL net table is developed based on Rapidsmith. The single particle soft error sensitivity analysis for XC4VSX55 FPGA systems is supported at present. (2) the analysis of FPGA resources in XDL net tables. In this paper, the FPGA resources described by the XDL net table are studied, the description of the sensitive resources in the XDL net table is interpreted, the syntax structure of the XDL net table is expounded, and the corresponding relation between the description content and the underlying circuit resources of FPGA is analyzed in detail. It strengthens people's cognition of XDL net tables and FPGA resources, and makes up for the shortcomings of unclear description of this kind of content in China. (3) parsing of FPGA resources in configuration files. This paper completes the mapping relationship between FPGA resources and configuration bits described in the XDL net table, corrects the errors of frame address arrangement of XC4VSX55 chips published on Xilinx official network, and further explores the corresponding relationship between PIPs resources and configuration bits, and analyzes the frame structure. The configuration data of XC4VSX55 chip is basically analyzed, and the research method is universal and suitable for Virtex-5 and higher series chips.
【學(xué)位授予單位】：國(guó)防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：V441;TN791

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本文編號(hào)：2294138