高速高精度流水線ADC中運(yùn)算放大器的設(shè)計(jì)
發(fā)布時(shí)間：2018-10-20 11:16
【摘要】：自從美國(guó)德州儀器公司的杰克2基爾比在1958年向人們展示了第一塊集成電路以來,集成電路作為一份全新的產(chǎn)業(yè)誕生了。在過去的50多年中,電子產(chǎn)品,特別是以集成電路芯片為核心的電子產(chǎn)品層出不窮。隨著時(shí)代的進(jìn)步,人們對(duì)電子產(chǎn)品的性能要求越來越高,這也就對(duì)集成電路芯片的性能提出了更高的要求。作為構(gòu)成模擬系統(tǒng)和數(shù)�；旌舷到y(tǒng)的重要基本單元,算放大器如何設(shè)計(jì)和優(yōu)化運(yùn),是整個(gè)芯片系統(tǒng)設(shè)計(jì)中的重要內(nèi)容。ADC(模擬-數(shù)字轉(zhuǎn)換器),作為連接模擬信號(hào)和數(shù)字信號(hào)的橋梁,在數(shù)字電路和數(shù)字信號(hào)處理技術(shù)高速發(fā)展的今天,重要性越來越突出。流水線ADC(Pipelined ADC)是高速高精度ADC設(shè)計(jì)中普遍選用的結(jié)構(gòu),因?yàn)樗芎芎玫募骖櫵俣�、功耗、面積等方面的要求。在流水線ADC電路結(jié)構(gòu)中,核心模塊之一就是運(yùn)算放大器,它的性能對(duì)流水線ADC的最終性能有直接的影響。因此,研究和設(shè)計(jì)高增益、寬帶寬的運(yùn)算放大器對(duì)實(shí)現(xiàn)高速精度流水線ADC意義重大。本文首先設(shè)計(jì)了一款應(yīng)用于流水線ADC中的全差分兩級(jí)運(yùn)算放大器,第一級(jí)電路采用了折疊式共源共柵結(jié)構(gòu),第二級(jí)電路則選用了簡(jiǎn)單共源放大結(jié)構(gòu)。為了穩(wěn)定輸出共模電壓,在兩級(jí)中都加入了共模負(fù)反饋電路,其中第一級(jí)使用了結(jié)構(gòu)簡(jiǎn)單但很有效的交叉耦合負(fù)反饋。在仿真驗(yàn)證了設(shè)計(jì)的正確性之后,進(jìn)行了版圖的設(shè)計(jì)。仿真結(jié)果顯示所設(shè)計(jì)的運(yùn)算放大器直流增益為92.8 d B,單位增益帶寬為195.5 MHz。該設(shè)計(jì)采用TSMC0.18μm 1P6M工藝流片實(shí)現(xiàn),并設(shè)計(jì)了用于測(cè)試的電路板對(duì)實(shí)際的芯片進(jìn)行了測(cè)試,測(cè)試結(jié)果顯示運(yùn)算放大器直流增益為83 d B,單位增益帶寬為170 MHz。針對(duì)一款14bit 100MS/s流水線ADC的設(shè)計(jì)要求,本文采用增益自舉(Gain-boosting)結(jié)構(gòu)設(shè)計(jì)了一款單級(jí)共源共柵運(yùn)算放大器,在不改變?cè)\(yùn)算放大器的直流工作狀態(tài)的情況下,增益自舉技術(shù)能大大提高運(yùn)算放大器的增益。在仿真驗(yàn)證了設(shè)計(jì)的正確性之后,進(jìn)行了版圖的設(shè)計(jì)。仿真結(jié)果顯示所設(shè)計(jì)的運(yùn)算放大器直流增益為100.6 d B,單位增益帶寬為968.9 MHz。
[Abstract]:Since Jack 2 Kilby of Texas Instruments showed the first integrated circuit in 1958, integrated circuit has been born as a new industry. In the past 50 years, electronic products, especially IC chips as the core of electronic products emerge in endlessly. With the progress of the times, the performance requirements of electronic products are becoming higher and higher, which puts forward higher requirements for the performance of integrated circuit chips. As an important basic unit of analog system and digital-analog hybrid system, how to design and optimize the amplifier is calculated. As a bridge between analog signal and digital signal,. ADC (is an important content in the whole chip system design. With the rapid development of digital circuit and digital signal processing technology, the importance is more and more prominent. Pipelined ADC (Pipelined ADC) is a widely used structure in high speed and high precision ADC design, because it can take into account the requirements of speed, power consumption, area and so on. In the pipelined ADC circuit structure, one of the core modules is the operational amplifier. Its performance has a direct impact on the final performance of the pipeline ADC. Therefore, it is of great significance to study and design high gain and wide bandwidth operational amplifiers to achieve high speed precision pipeline ADC. In this paper, a fully differential two-stage operational amplifier used in pipelined ADC is designed. The first stage of the circuit adopts a folded common-source common-gate structure, and the second stage of the circuit uses a simple common-source amplifier. In order to stabilize the output common-mode voltage, a common-mode negative feedback circuit is added in both stages. In the first stage, a simple but effective cross-coupled negative feedback is used. After the correctness of the design is verified by simulation, the layout is designed. The simulation results show that the DC gain of the operational amplifier is 92.8 dB and the unit gain bandwidth is 195.5 MHz.. The design is implemented by TSMC0.18 渭 m 1P6M technology, and the circuit board used for testing is designed to test the actual chip. The test results show that the DC gain of the operational amplifier is 83 dB and the unit gain bandwidth is 170 MHz.. According to the design requirements of a 14bit 100MS/s pipelined ADC, a single-stage common-grid operational amplifier is designed using gain bootstrap (Gain-boosting) structure, without changing the DC operating state of the original operational amplifier. The gain bootstrap technique can greatly improve the gain of operational amplifier. After the correctness of the design is verified by simulation, the layout is designed. The simulation results show that the DC gain of the operational amplifier is 100.6 dB and the bandwidth per unit gain is 968.9 MHz..
【學(xué)位授予單位】：深圳大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN722.77;TN792
本文編號(hào)：2282992
[Abstract]:Since Jack 2 Kilby of Texas Instruments showed the first integrated circuit in 1958, integrated circuit has been born as a new industry. In the past 50 years, electronic products, especially IC chips as the core of electronic products emerge in endlessly. With the progress of the times, the performance requirements of electronic products are becoming higher and higher, which puts forward higher requirements for the performance of integrated circuit chips. As an important basic unit of analog system and digital-analog hybrid system, how to design and optimize the amplifier is calculated. As a bridge between analog signal and digital signal,. ADC (is an important content in the whole chip system design. With the rapid development of digital circuit and digital signal processing technology, the importance is more and more prominent. Pipelined ADC (Pipelined ADC) is a widely used structure in high speed and high precision ADC design, because it can take into account the requirements of speed, power consumption, area and so on. In the pipelined ADC circuit structure, one of the core modules is the operational amplifier. Its performance has a direct impact on the final performance of the pipeline ADC. Therefore, it is of great significance to study and design high gain and wide bandwidth operational amplifiers to achieve high speed precision pipeline ADC. In this paper, a fully differential two-stage operational amplifier used in pipelined ADC is designed. The first stage of the circuit adopts a folded common-source common-gate structure, and the second stage of the circuit uses a simple common-source amplifier. In order to stabilize the output common-mode voltage, a common-mode negative feedback circuit is added in both stages. In the first stage, a simple but effective cross-coupled negative feedback is used. After the correctness of the design is verified by simulation, the layout is designed. The simulation results show that the DC gain of the operational amplifier is 92.8 dB and the unit gain bandwidth is 195.5 MHz.. The design is implemented by TSMC0.18 渭 m 1P6M technology, and the circuit board used for testing is designed to test the actual chip. The test results show that the DC gain of the operational amplifier is 83 dB and the unit gain bandwidth is 170 MHz.. According to the design requirements of a 14bit 100MS/s pipelined ADC, a single-stage common-grid operational amplifier is designed using gain bootstrap (Gain-boosting) structure, without changing the DC operating state of the original operational amplifier. The gain bootstrap technique can greatly improve the gain of operational amplifier. After the correctness of the design is verified by simulation, the layout is designed. The simulation results show that the DC gain of the operational amplifier is 100.6 dB and the bandwidth per unit gain is 968.9 MHz..
【學(xué)位授予單位】：深圳大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN722.77;TN792
【共引文獻(xiàn)】
相關(guān)期刊論文 前1條
1 黃偉;翟江輝;楊秋玉;康金星;;三通道高亮度LED驅(qū)動(dòng)芯片的ASIC設(shè)計(jì)[J];電子技術(shù)應(yīng)用;2015年04期
相關(guān)碩士學(xué)位論文 前7條
1 張祖翔;48dB動(dòng)態(tài)范圍、37dBm-ⅡP_3的CMOS可變?cè)鲆娣糯笃髟O(shè)計(jì)[D];華中科技大學(xué);2013年
2 趙杰;基于CMOS升壓電路控制器設(shè)計(jì)[D];黑龍江大學(xué);2014年
3 孫文;一種低噪聲大動(dòng)態(tài)范圍小型前端電路的研究[D];中國(guó)科學(xué)院研究生院（近代物理研究所）;2014年
4 黃廷昭;一款高精度高線性度MEMS加速度計(jì)的研究與設(shè)計(jì)[D];北京工業(yè)大學(xué);2014年
5 趙宗良;0.18μm CMOS 6.25Gb/s模擬自適應(yīng)均衡器的研究與設(shè)計(jì)[D];南京郵電大學(xué);2014年
6 商龍;UHF RFID閱讀器發(fā)射機(jī)模擬基帶電路的研究與設(shè)計(jì)[D];南京郵電大學(xué);2014年
7 劉舒;電波鐘表專用接收系統(tǒng)的設(shè)計(jì)[D];哈爾濱工業(yè)大學(xué);2011年
，本文編號(hào)：2282992
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