FPGA功耗早期評估模型研究與實(shí)現(xiàn)
發(fā)布時(shí)間：2018-10-17 20:44
【摘要】：現(xiàn)場可編程門陣列(FPGA)由于其設(shè)計(jì)成本低、可重復(fù)編程等優(yōu)點(diǎn)被廣泛應(yīng)用。隨著工藝進(jìn)入納米尺寸,FPGA集成度越來越高,導(dǎo)致設(shè)計(jì)的功耗問題更加突出。商用FPGA功耗評估工具包括Xpower和EPE,其中Xpower在布局布線后進(jìn)行功耗評估,結(jié)果精確；EPE在設(shè)計(jì)早期評估功耗,精度不高。其他的功耗評估研究工作在設(shè)計(jì)不同層次進(jìn)行,也存在精度不高的問題。本文對FPGA功耗早期評估進(jìn)行了建模與實(shí)現(xiàn)。在介紹了FPGA架構(gòu)和功耗來源的基礎(chǔ)上,考慮到商用FPGA電路結(jié)構(gòu)的復(fù)雜性,本文在電路綜合完成后對FPGA功耗進(jìn)行評估,將FPGA功耗分為可編程邏輯資源和時(shí)鐘／互連資源功耗,并分別對兩部分功耗進(jìn)行建模。對于可編程邏輯資源,建立了基于開關(guān)活動性和資源使用數(shù)的動態(tài)宏單元功耗模型。其中設(shè)計(jì)了基于ARMA信號的隨機(jī)激勵(lì)產(chǎn)生器,并使用基于概率傳遞的方法評估電路開關(guān)活動性,通過編寫perl腳本解析網(wǎng)表獲取資源使用數(shù)。對于時(shí)鐘／互連部分,在分析單條互連功耗隨模塊間距離線性增加的基礎(chǔ)上,建立了基于面積估算的開關(guān)級功耗模型。其中為了抽取不同類型互連的等效電容,本文采用一種基于差值和非線性擬合的方法。此外,為了驗(yàn)證功耗模型的正確性,本文搭建了仿真驗(yàn)證平臺,對Virtex-6 XC6VLX760芯片進(jìn)行功耗評估。該平臺讀入綜合后的網(wǎng)表文件和激勵(lì)信號,計(jì)算電路節(jié)點(diǎn)開關(guān)活動性和資源使用數(shù)。對MCNC的20個(gè)基準(zhǔn)電路分別采用本文模型與Xpower軟件的結(jié)果進(jìn)行對比,表明上述模型的最小誤差為3.62%,最大誤差為45.3%,平均誤差為22.8%。與同類文獻(xiàn)對比實(shí)驗(yàn)結(jié)果顯示,在抽象層次相同的情況下本文模型精度比同類文獻(xiàn)高15%,表明本文功耗模型能夠精確的評估功耗。
[Abstract]:Field Programmable Gate Array (FPGA) is widely used because of its low design cost and repeatable programming. As the process enters into nanometer size, the integration of FPGA becomes more and more high, which leads to the problem of design power consumption becoming more and more prominent. Commercial FPGA power evaluation tools include Xpower and EPE, where Xpower is used to evaluate power consumption after layout and wiring, and EPE is used to evaluate power consumption in the early stage of design. Other research work on power evaluation is carried out at different levels of design, which also has the problem of low precision. In this paper, the early evaluation of FPGA power consumption is modeled and implemented. Based on the introduction of FPGA architecture and power source, considering the complexity of the circuit structure of commercial FPGA, this paper evaluates the power consumption of FPGA after circuit synthesis, and divides the power consumption of FPGA into programmable logic resources and clock / interconnect resources power consumption. The two parts of power consumption are modeled separately. For programmable logic resources, a dynamic macro cell power model based on switch activity and resource usage is established. A random excitation generator based on ARMA signal is designed, and the probability transfer based method is used to evaluate the switch activity of the circuit. The perl script is written to analyze the network table to obtain the resource usage. For the clock / interconnect part, a switching level power model based on area estimation is established on the basis of analyzing that the power consumption of single interconnect increases linearly with the distance between modules. In order to extract the equivalent capacitance of different types of interconnection, a method based on difference and nonlinear fitting is used in this paper. In addition, in order to verify the correctness of the power model, a simulation verification platform is built to evaluate the power consumption of Virtex-6 XC6VLX760 chip. The platform reads the network table file and the excitation signal, calculates the switch activity and the resource usage of the circuit node. The results of 20 reference circuits of MCNC are compared with the results of Xpower software. The results show that the minimum error of the above model is 3.622, the maximum error is 45.3 and the average error is 22.8. The experimental results show that the accuracy of the proposed model is 15% higher than that of the similar literatures under the same abstraction level, which indicates that the proposed model can accurately evaluate the power consumption.
【學(xué)位授予單位】：東南大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2016
【分類號】：TN791
本文編號：2277916
[Abstract]:Field Programmable Gate Array (FPGA) is widely used because of its low design cost and repeatable programming. As the process enters into nanometer size, the integration of FPGA becomes more and more high, which leads to the problem of design power consumption becoming more and more prominent. Commercial FPGA power evaluation tools include Xpower and EPE, where Xpower is used to evaluate power consumption after layout and wiring, and EPE is used to evaluate power consumption in the early stage of design. Other research work on power evaluation is carried out at different levels of design, which also has the problem of low precision. In this paper, the early evaluation of FPGA power consumption is modeled and implemented. Based on the introduction of FPGA architecture and power source, considering the complexity of the circuit structure of commercial FPGA, this paper evaluates the power consumption of FPGA after circuit synthesis, and divides the power consumption of FPGA into programmable logic resources and clock / interconnect resources power consumption. The two parts of power consumption are modeled separately. For programmable logic resources, a dynamic macro cell power model based on switch activity and resource usage is established. A random excitation generator based on ARMA signal is designed, and the probability transfer based method is used to evaluate the switch activity of the circuit. The perl script is written to analyze the network table to obtain the resource usage. For the clock / interconnect part, a switching level power model based on area estimation is established on the basis of analyzing that the power consumption of single interconnect increases linearly with the distance between modules. In order to extract the equivalent capacitance of different types of interconnection, a method based on difference and nonlinear fitting is used in this paper. In addition, in order to verify the correctness of the power model, a simulation verification platform is built to evaluate the power consumption of Virtex-6 XC6VLX760 chip. The platform reads the network table file and the excitation signal, calculates the switch activity and the resource usage of the circuit node. The results of 20 reference circuits of MCNC are compared with the results of Xpower software. The results show that the minimum error of the above model is 3.622, the maximum error is 45.3 and the average error is 22.8. The experimental results show that the accuracy of the proposed model is 15% higher than that of the similar literatures under the same abstraction level, which indicates that the proposed model can accurately evaluate the power consumption.
【學(xué)位授予單位】：東南大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2016
【分類號】：TN791
【相似文獻(xiàn)】
相關(guān)會議論文 前1條
1 趙林芳;;血管通路早期評估[A];全國靜脈輸液治療護(hù)理學(xué)術(shù)交流會議論文匯編[C];2012年
相關(guān)碩士學(xué)位論文 前5條
1 唐勇;譫妄早期評估及干預(yù)對急診重癥患者臨床結(jié)局的影響[D];蘭州大學(xué);2015年
2 徐凱;FPGA功耗早期評估模型研究與實(shí)現(xiàn)[D];東南大學(xué);2016年
3 鐘峗;多發(fā)性骨髓瘤腎損害的早期評估[D];第二軍醫(yī)大學(xué);2012年
4 張雨婷;新生兒缺氧缺血性腦病合并腎臟功能損害的早期評估[D];重慶醫(yī)科大學(xué);2009年
5 唐梅麗;DTI及FT對HIE早期和后期復(fù)查的對照研究及預(yù)后的早期評估[D];暨南大學(xué);2007年
，本文編號：2277916
本文鏈接：http://sikaile.net/kejilunwen/dianzigongchenglunwen/2277916.html
最近更新
教材專著
